Hi Wan.We use the Xilinx Memory Interface Generator (MIG) 2.3 through COREGEN to generate our controller.
The generated code is in the CASPER svn at:
mlib_devel_10_1/xps_lib/XPS_ROACH_base/pcores/dram_controller_v1_00_a/hdl/verilog Regards, -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: [email protected] Web: www.ska.ac.za
