Hi David: Thanks for your answer. But I am afraid this core is not included into the released 10.1 library. Could you please email this core to me?
Thanks Wan -----Original Message----- From: David George [mailto:david.geo...@ska.ac.za] Sent: Wednesday, 14 January 2009 5:18 PM To: Cheng, Wan (ATNF, Marsfield); casper@lists.berkeley.edu Subject: DRAM on ROACH Hi Wan. We use the Xilinx Memory Interface Generator (MIG) 2.3 through COREGEN to generate our controller. The generated code is in the CASPER svn at: mlib_devel_10_1/xps_lib/XPS_ROACH_base/pcores/dram_controller_v1_00_a/hdl/verilog Regards, -- David George Digital Design Engineer Karoo Array Telescope Tel: +27 21 531-7282 Fax: +27 21 531-9761 Email: david.geo...@ska.ac.za Web: www.ska.ac.za
