Yes, Dave tracked down the confusion... I was using an old version of
the yellow block which still had this parameter as an option (even
though we don't believe it was ever implemented).
My BEE2 designs are using between 94 and 99% logic... hence my
problems :)
Though even with designs around 75%, I pick up intermittent DRAM
timing issues.
Jason
On 01 Apr 2009, at 14:30, G Jones wrote:
Hi Jason and David,
As David pointed out, the 7.1 version of the libraries (or at least
the ones I'm using) do not have the "Share w/ PPC" box. My design
uses all 4 XAUI interfaces, 4 DIMMS at 200 MHz, and 60 interchip
interconnects to buffer XAUI data and then send it over the
interchip interconnects to another FPGA with a 10 GbE block to a
computer when a trigger occurs. All of this is controlled with state
machines (implemented with mcode blocks) and FIFOs. The "simulink"
clock is 200 MHz. The design uses 53% of slices (33% FFs and 23%
LUTs) and 62% BRAMs so the chip isn't that densely packed, but in
the floorplan view it looks quite full. It definitely took a few
iterations to meet timing. David, thanks for the info, I
misunderstood and thought the async_ddr2 was part of the sniffer. I
will look into making the change to the pcore you suggest.
Thanks,
Glenn
On Tue, Mar 31, 2009 at 11:25 PM, Jason Manley
<[email protected]> wrote:
Isn't that what the "Share with PPC" box in the simulink mask dialog
is for? Is it not workin?
BTW, how did you manage to get all four controllers to meet timing?
Or are you not running at 200MHz? Unless the FPGA is all but empty,
I battle to get even two workin!
On 01 Apr 2009, at 05:52, G Jones wrote:
Hello,
I have a design which uses all four DIMMs on a BEE2 User FPGA. I
have no need to access the DIMMs from BORPH or the PowerPC, and it
seems like the interfaces to do so take up a fair amount of
resources. Is there any (not too painful) way to remove those
interfaces to free up the resources?
Thanks,
Glenn
