Hi Glenn.
You can save some brams with a relatively simple change in the
async_ddr2 pcore. If you replace the existing bram fifos (512 deep) with
distributed memory (16 deep) you save a number of brams (7, I think).
There is also a substantial timing improvement. With ROACH in 10.1 this
option is configurable through a yellow block checkbox and a pcore
parameter.
I've had a quick look at the 7.1 BEE2 DRAM CPU interface (the sniffer,
as it is called), and that module seems to use only distributed ram and
a little logic. I could be wrong though. Also it looks as though the
"share with PPC" checkbox doesn't do anything on 7.1 and was recently
removed. This option works on ROACH 10.1 though.
Cheers,
David
I have a design which uses all four DIMMs on a BEE2 User FPGA. I have
no need to access the DIMMs from BORPH or the PowerPC, and it seems
like the interfaces to do so take up a fair amount of resources. Is
there any (not too painful) way to remove those interfaces to free up
the resources?
Thanks,
Glenn
--
David George
Digital Design Engineer
Karoo Array Telescope
Tel: +27 21 531-7282
Fax: +27 21 531-9761
Email: [email protected]
Web: www.ska.ac.za
