Hi Wan,
The ADC control pins are part of the ADC controller pcore, rather
than the ADC interface pcore. The controller and its constraints
are conditionally written into the project files during preprocessing.
There should be a small block in the UCF file somewhere before all
of the other ADC constraints labeled "ADC Control Signals". These
pins are defined directly in the base system's default UCF file.
-Henry
[email protected] wrote:
Hi David:
Thanks you for your help. I rebuild my design today. It seems all right now. I
can read valid data from all diff pairs.
I might not do right thing in the first build. Thanks for your information
again.
By the way, the in capsper 10.1 trunk, I did not find the pin allocation for
the 3 wire contrl pins. Where are they defined?
The following lines I insert into my UCF file:
# ADC card 3 wire control
NET "adc0_adc3wire_clk" IOSTANDARD = LVCMOS25 | LOC = F28;
NET "adc0_adc3wire_data" IOSTANDARD = LVCMOS25 | LOC = D32;
NET "adc0_adc3wire_strobe" IOSTANDARD = LVCMOS25 | LOC = C32;
NET "adc0_modepin" IOSTANDARD = LVCMOS25 | LOC = E28;
Thanks
Wan
-----Original Message-----
From: [email protected] [mailto:[email protected]] On Behalf Of David
George
Sent: Thursday, 18 June 2009 7:06 PM
To: Cheng, Wan (ATNF, Marsfield)
Cc: [email protected]
Subject: Re: [casper] problem of ADC 1.1 card with Roach
Hi Wan.
I find ADC chip is not set into a right mode because only 2 of 4 diff pairs
give me right data. So I find the 3 wire control pins are not allocated in
the UCF file. I modify the UCF file according to the schematic.
Compare your pin constraints to those in the casper subversion
repository, specifically the ucf file at:
mlib_devel_10_1/xps_lib/XPS_ROACH_base/data/system.ucf. Perhaps it
would be a good idea to rebuild your design using an up-to-date casper
toolflow.
I'm not quite sure what you mean by "2 of the 4 diff pairs". Are you
seeing what looks like sensible data on two of the four byte lanes
from a single ADC channel?
But I find I still could not get right data and I could not find right clock
from the 3 wire control clock.
I don't follow. Are you probing the three wire interface on the ADC
and are not seeing a clock or data?
I setup the FPGA clock coming from ADC card. So I think my fabric clock
should be 1/2 or 1/4 sample rate clock depending on the configuration of ADC
chip. Now I provide a 400MHz sample rate clock to the ADC card.
You should expect the FPGA clock rate to be 1/4 (100MHz) with a
configured iADC, 1/2 indicates that the iADC has not been configured
correctly.
I have not made sense that what the counter you mentioned is? What's the
function?
I suggest you set up an led-flasher in your simulink design so you can
see that the clock is alive.
Any idea about my problem? I think, basically, the problem is the ADC chip
is not configured correctly.
I agree. As before I suggest you rebuild your design with an
up-to-date svn. I will build a basic adc design to test the toolflow
and see if I have these problems. (I'm off sick so it won't be today,
perhaps tomorrow)
Regards,
David
