> On 10GbEv2 it is 8192, plus UDP and IP headers etc. But there would be > no space for your application headers. > > When we specc'd it originally, the thought here was that 8192b is the > closest power-of-2 for BRAM sizing to that same 9216b limit for most > NICs. If we wanted to get to 9000, we'd have to double the BRAM size > to 16k. And my applications are usually BRAM limited, so I was out to > save every one I could.
This is a reasonable decision. > > On the old Xilinx core, I seem to recall success with packet sizes up > to 1100x64b. But this was a long time ago. So this might work for you, > but YMMV. Thanks. We will want to have our system ready to migrate forward, so we will not push the packet payload past 8192 bytes. John > > Jason > > On 22 Jun 2009, at 13:16, John Ford wrote: > >> Hi. Does anybody know the actual limit on packet size for the >> original xilinx and the V2 10 GbE cores? The documents say something >> vague like "about 8k bytes", but is there a known hard limit to the >> packet >> size in each case? >> >> We want to package up 8K (8192) bytes of data + a few words of >> framing, >> plus the Ethernet and IP headers the core sticks on. I know we want >> the >> whole packet less than 9000 bytes, since that's what some of our >> hosts use >> as the jumbo MTU. It would be convenient if the whole mess would go >> in >> one large packet. >> >> Thanks. >> >> John >> >> >> >> >
