Hi All.
On 10GbEv2 it is 8192, plus UDP and IP headers etc. But there would be
no space for your application headers.
This is correct, 8k is the V2 limit. There are a few problems with the
current implementation, firstly it would be far more useful to support
8k data payload + some control/status info, which, I gather, is what you
would like to do. Also the core will start telling you the fifo is
always tell you that it is almost full for every packet, which makes
backing off impossible. For these reasons I would like to add a 32
entries distributed ram augmentation fifo, to extend the capacity by 32
entries (32*8 bytes) without requiring an extra bram. Apologies for the
lousy documentation, I have a knack at writing vague documents.
I will have a go at getting this done tomorrow, I'll post when it looks
ready.
On the old Xilinx core, I seem to recall success with packet sizes up
to 1100x64b. But this was a long time ago. So this might work for you,
but YMMV.
The old core can do 16k (less a few) packets, hence the high bram
utilization.
Cheers,
David
--
David George
Digital Design Engineer
Karoo Array Telescope
Tel: +27 21 531-7282
Fax: +27 21 531-9761
Email: [email protected]
Web: www.ska.ac.za
