On Nov 12, 2009, at 16:36 , John Ford wrote:
At least one timing constraint is impossible to meet because component delays alone exceed the constraint.
I think this means that part of your design synthesized to multiple levels of combinatorial logic where the sum of each level's component delay alone (i.e. not even counting propagation delay from component to component) exceed the period of the clock.
You'll need to create a timing report (e.g. using trce) to find out which part of the design is problematic.
Dave
