hi john,
glenn jones is working with terry filiba today on improving the speed
of the corner turn in the FFT. stay tuned.
dan
Hi John
Some pointers on improving timing generally in ROACH.
Decrease the space your design occupies. Implement delays on data
inputs to multiplier cores in behavioural logic as these are absorbed
by the DSP48E core. Implement large adders and counters in DSP48Es.
Use Truncation as your Rounding strategy where possible (decreases
timing pressure on the FFT especially).
Increase BRAM delays or place delays between BRAM outputs and logic.
The links between BRAMs and multiplier cores or other BRAMs are
especially troublesome.
Try to implement logic as a pipeline with minimal "closed loop"
feedback paths. This allows latency to increase performance to be
added arbitrarily without necessitating a remake of the logic.
Good luck
Regards
Andrew
2009/11/13 John Ford <jf...@nrao.edu <mailto:jf...@nrao.edu>>
>
> On Nov 12, 2009, at 16:36 , John Ford wrote:
>
>> At least one timing constraint is impossible to meet because
>> component delays alone exceed the constraint.
>
> I think this means that part of your design synthesized to multiple
> levels of combinatorial logic where the sum of each level's
component
> delay alone (i.e. not even counting propagation delay from component
> to component) exceed the period of the clock.
>
> You'll need to create a timing report (e.g. using trce) to find out
> which part of the design is problematic.
I managed to figure out how to use the timing analyser in this
version,
and it's clear to me now that the message that's output is pretty
misleading. It's got nothing really to do with the ADC, it's just
that
that's the clock signal that everything's clocked off of. The
real timing
errors are in the FFT and some arithmetic. Hopefully with a little
adjustment to some latencies I can make it meet timing.
Thanks for the info.
John
>
> Dave
>
