Hi Dan: Thanks for your suggestions.
I believe we get enough SNR and dynamic range. We just suspect if there are some potential problems in our design. Calibration is our current solution, and I believe it will work well in our system. And I tried all different rounding options, I found round +/- inf is the best, even better than round even or odd. Is this normal? For wider bit width in FFT, I remember over 18 bits could not work properly. So now it is fixed and it can work upto 25 bits? Thanks, Dan. Wan ________________________________ From: Dan Werthimer [mailto:[email protected]] Sent: Thursday, 14 January 2010 11:54 AM To: Cheng, Wan (CASS, Marsfield) Cc: [email protected] Subject: Re: [casper] DC part of FFT output hi wan, here are five steps you could take, if you haven't already, to raise your signal higher above the noise floor and increase dynamic range: -1) adjust the FFT shifter settings to boost the output signal so it's in the MSB's, way above the pattern noise. 0) subtract out the fixed pattern noise in post processing/calibration. (this might be tricky, as it might be signal level dependent??) this is easiest done after the FPGA (in C or some other high level language). 1) raise the signal amplitude, so SNR will be higher 2) use more bits in the FFT. i think with virtex 5, you can go to 25 bits. (this takes more FFT resources) 3) turn on rounding in the FFT (this takes more FPGA resources). the best rounding to use is round to even, or round to odd. (not round up, or round down). i'm not sure what kind of rounding we used in the FFT. best wishes, dan On 1/13/2010 3:31 PM, [email protected]<mailto:[email protected]> wrote: Hi Dan: Thanks a lot. I also believe it is from round off noise. But it does not just occupy the least significant bit. I guess, because there are a number of stages in PFB and FFT, the round off noise will be distributed and accumulated at every stage. So at the final output, it would not just least significant bit any more. For a 1024 points FFT, I believe it could occupy 6 bits of 36 bits output. But they are still relative very small compared with the main carrier output. Please see the attached(steps2) for details about the noise floor. Our problem is we are using a 32K FFT, a fixed pattern become obvious on noise floor after we integrate for 1 sec. Please see the attached for 32K FFT noise floor. The pattern on noise floor is fixed, it would not change with the input. So is there any way we could remove or minimize the steps on noise floor? Thanks Wan ________________________________ From: Dan Werthimer [mailto:[email protected]] Sent: Wednesday, 13 January 2010 2:37 PM To: [email protected]<mailto:[email protected]> Subject: Re: [casper] DC part of FFT output hi wan, what are the levels of this output? if they are the least significant bits, then this is likely from round off noise. best wishes, dan On 1/12/2010 6:45 PM, [email protected]<mailto:[email protected]> wrote: Hi All: I use a matlab sine wave generator to generate a sine wave as an input to PFB and FFT. But I find I get a little DC output and a few small steps from FFT output. I am pretty sure there is no DC added into the input signal. So where these DC could be from? And why there is some small steps on the noise floor? For the details of spectrum output, please see the attached. Thanks Wan
