hi wan,
regarding shifter settings to optimize dynamic range:
(this is important for long FFT's)
for coherent signals (pure sine/cos wave), you need to downshift at
every FFT stage
to prevent overflow, since coherent signals grow by 2 every stage.
pure noise signals grow by sqrt(2) every stage,
so one should downshift at every other stage for maximum dynamic range.
for signals in between pure noise and pure sine waves, (eg: radio
telescope data
with some RFI), to get maximum dynamic range, it's good to shift somewhere
in between these two extremes, and it's good to turn the first stage
shifter on,
(depending on how strong your input signal is).
perhaps:
1st stage: down-shift
2nd: down-shift
3rd: no shift
4-6: repeat of stage 1-3.
7-9: repeat of stage 1-3
....
dan
On 1/14/2010 2:34 PM, wan.ch...@csiro.au wrote:
Hi Jason:
Thanks for your important information.
But one point I could not understand is the shift bits of FFT.
I guess it is used to shift the output at every FFT stage. So why data only in
top 10 bits? 10 bits data multiplies 8 bits coeff, the data should be in all 18
bits?
Wan
-----Original Message-----
From: Jason Manley [mailto:jasonman...@gmail.com]
Sent: Thursday, 14 January 2010 5:46 PM
To: Cheng, Wan (CASS, Marsfield)
Cc: d...@ssl.berkeley.edu; casper@lists.berkeley.edu
Subject: Re: [casper] DC part of FFT output
We (KAT) use:
* Round +-even in FFT and PFB.
* Bitwidth at 18bits. Multipliers are 18x25 in V5, not 25x25.
* Using lower bitwidths for lookup table in PFB does not have a
major impact on performance (eg, PAPER is using 8 bit lookups).
* There is support for different coeff bitwidths and signal
bitwidths in the FFT and PFB. If you need more bits, consider 25 bits
I/O and 18 bits ceoffs. While still needing more routing resources,
you will not need more multipliers.
* It is critical that you position your signal properly and set FFT
shift pattern correctly. For most applications, you will position your
input signal in the (top bit -1) of your FFT and downshift on every
stage (all 1's in the fft_shift input). But for a 32k FFT, you would
then have 15 bits of downshift. With your signal in the top 10 bits of
an 18 bit number, you will shift out 18-10-15 = -7 and hence lose
data. So in this case, you'd probably want to shift on every second
stage or something. This would ensure that you're never shifting data
out the bottom, but now you need to be careful that you're not
overflowing on any FFT stage. Check the 'of' port; though not aligned
with the data, it will report if an overflow did occur at some point.
Jason
On 14 Jan 2010, at 03:07,<wan.ch...@csiro.au> <wan.ch...@csiro.au>
wrote:
Hi Dan:
Thanks for your suggestions.
I believe we get enough SNR and dynamic range. We just suspect if
there are some potential problems in our design. Calibration is our
current solution, and I believe it will work well in our system.
And I tried all different rounding options, I found round +/- inf is
the best, even better than round even or odd. Is this normal?
For wider bit width in FFT, I remember over 18 bits could not work
properly. So now it is fixed and it can work upto 25 bits?
Thanks, Dan.
Wan
From: Dan Werthimer [mailto:d...@ssl.berkeley.edu]
Sent: Thursday, 14 January 2010 11:54 AM
To: Cheng, Wan (CASS, Marsfield)
Cc: casper@lists.berkeley.edu
Subject: Re: [casper] DC part of FFT output
hi wan,
here are five steps you could take, if you haven't already,
to raise your signal higher above the noise floor and increase
dynamic range:
-1) adjust the FFT shifter settings to boost the output
signal so it's in the MSB's, way above the pattern noise.
0) subtract out the fixed pattern noise in post processing/
calibration.
(this might be tricky, as it might be signal level dependent??)
this is easiest done after the FPGA (in C or some other high
level language).
1) raise the signal amplitude, so SNR will be higher
2) use more bits in the FFT. i think with virtex 5, you can go to
25 bits.
(this takes more FFT resources)
3) turn on rounding in the FFT (this takes more FPGA resources).
the best rounding to use is round to even, or round to odd.
(not round up, or round down).
i'm not sure what kind of rounding we used in the FFT.
best wishes,
dan
On 1/13/2010 3:31 PM, wan.ch...@csiro.au wrote:
Hi Dan:
Thanks a lot. I also believe it is from round off noise.
But it does not just occupy the least significant bit. I guess,
because there are a number of stages in PFB and FFT, the round off
noise will be distributed and accumulated at every stage. So at the
final output, it would not just least significant bit any more. For
a 1024 points FFT, I believe it could occupy 6 bits of 36 bits
output. But they are still relative very small compared with the
main carrier output. Please see the attached(steps2) for details
about the noise floor.
Our problem is we are using a 32K FFT, a fixed pattern become
obvious on noise floor after we integrate for 1 sec. Please see the
attached for 32K FFT noise floor. The pattern on noise floor is
fixed, it would not change with the input. So is there any way we
could remove or minimize the steps on noise floor?
Thanks
Wan
From: Dan Werthimer [mailto:d...@ssl.berkeley.edu]
Sent: Wednesday, 13 January 2010 2:37 PM
To: casper@lists.berkeley.edu
Subject: Re: [casper] DC part of FFT output
hi wan,
what are the levels of this output?
if they are the least significant bits,
then this is likely from round off noise.
best wishes,
dan
On 1/12/2010 6:45 PM, wan.ch...@csiro.au wrote:
Hi All:
I use a matlab sine wave generator to generate a sine wave as an
input to PFB and FFT.
But I find I get a little DC output and a few small steps from FFT
output. I am pretty sure there is no DC added into the input
signal. So where these DC could be from?
And why there is some small steps on the noise floor?
For the details of spectrum output, please see the attached.
Thanks
Wan
