hi rick,
the 10GBe block incorporates multiple clock domain logic already:
you can send your data into the 10Ggbe block at any fpga clock rate
(since the 10Gbe block has fifo's inside) and the 10Gbe block will
transmit
your data using it's internal 156.25 MHz clock. you must take
care not to overflow the 10Gbe block's internal fifo's - eg: the long term
average data rate that you send into the 10Gbe block must not exceed
10Gbit/sec,
although you can send in burst data rates higher than 10gbit/sec
and the internal fifo's will smooth out the data rate. some designs
send data
into the 10Gbe block every clock, some every other clock, some 3 out of
4 clocks,
some asychonously, determined by various states and flags...
best wishes,
dan
On 4/29/2010 2:11 PM, Rick Raffanti wrote:
Hi Casperians,
Can anyone point me in the right direction for building a simulink
design with multiple clock domains? SPecifically, I want to bring in
a data stream at one rate using an external source-synchronous clock,
and load it into the 10GbE block at the 156.25 MHz clock that
requires. From browsing around, I'm thinking I should maybe use the
"FromFIFO" and "ToFIFO" blocks.
Thanks for any help.
Rick
