I have a remotely located sensor which outputs digital data in two
28-bit-wide streams, each with a source-sync clock at 112.5MHz DDR, so
12.6 Gbits/sec burst rate, but much lower average. The data and clock
are bursty- the clock bursts when data is coming out, then stops. I
can't run the entire FPGA on this clock because it stops. And I can't
connect the output from this domain to the 10GbE inputs, I believe,
because the 10GbE input side runs at the FPGA fabric clock freq.
I think I need to make a new yellow block for this input stream. The
HDL to code this is pretty simple, I just need to connect it to the
right ZDOK pairs.
Any thoughts, anyone?
Thanks,
Rick
Billy Mallard wrote:
How are you getting this data stream into the board? It sounds like
you're not using an ADC. Are you using a custom ZDOK board with a
custom yellow block? Where is your clock coming from?
If the yellow block for your input device has a data line and a valid
line, you should be able to wire those directly to the corresponding
inputs on the 10GbE yellow block.
Billy
Rick Raffanti wrote:
Thanks, Billy.
In my situation I have a high-speed data stream coming in accompanied
by a clock which is not constant- it bursts when the data is coming
in, and stops other times. So I don't want to run the whole FPGA from
that. If I was just writing this in Verilog, I'd use a FIFO to cross
the clock domain from the burst clock to the FPGA clock, then pass the
data to the 10GbE block. But I don't see any way to tell the 10GbE
block that I'd like its input side to use my burst clock rather than
the system clock.
I'm coming to the conclusion that I need to make my input block into a
yellow block, and absorb the clock-domain-crossing FIFO into it.
Thanks,
Rick
Billy Mallard wrote:
Rick Raffanti wrote:
Can anyone point me in the right direction for building a simulink
design with multiple clock domains? SPecifically, I want to bring in
a data stream at one rate using an external source-synchronous clock,
and load it into the 10GbE block at the 156.25 MHz clock that
requires.
You don't need to use multiple clock domains to use the 10GbE block.
Afaik, the 10GbE yellow block already handles the clock mismatch for
you.
You do need to make sure that you're not feeding the yellow block at a
faster data rate than it can handle. If you do, you'll start seeing
tx_overflow go high.
Billy
