CC: list... > Hi Shrikanth, > > I haven't worked extensively with the DRAM, so i'm not sure why you would > be > getting these constant values. But I don't think half the data stored in > memory should be a constant.
Hi Srikanth. I wonder if this is because of DRAM size? It looks like an addressing flaw of some sort, which might be explained if our DRAM isn't the same size as the one used in the design used as a pattern? John > > The DRAM runs off a different clock then the FPGA and the read/write > schedule is a little tricky if I remember correctly. Do you need to be > using DRAM for what you're doing? > Have you compared your design to a known working one. > > Mark > > > On Thu, Sep 23, 2010 at 3:59 PM, bussa srikanth <[email protected]> wrote: > >> Hello Mr. Mark, >> >> How are you doing? >> >> I was able to plot the data from the DRAM. I saved the data in to a bin >> file and I used matlab to plot it. >> * >> Data Stream coming out of the DRAM appears to be like this:* >> >> -------------------First 16 Bytes >> ------------------------------------------- >> ------------------------------------- Second 16 Bytes >> -------------------------- -------------------------- Third 16 >> Bytes >> --------------------------------- >> '\x00\xfd\xfc\xfb\xfb\xfb\xfc\xfe\x80\x80\x80\x80\x80\x80\x80\x80 >> \x01\x02\x04\x04\x05\x03\x02\x00\x80\x80\x80\x80\x80\x80\x80\x80 >> \xfe\xfc\xfb\xfb\xfb\xfc\xfe\x01\x80\x80\x80\x80\x80\x80\x80\x80 ..... >> and >> so on.. >> >> For every 16 bytes the lower 8bytes appear to be constant. If I remove >> the >> constant data and plot it looks perfectly fine . The period of the sine >> wave >> what I am giving as input matches with the plot obtained from the DRAM >> data >> when I remove the lower 64 bits of data. >> >> I just wanted to know if that is the way the data is written in the >> DRAM.?? >> >> >> Thank you >> >> Regards, >> Srikanth >> >> >> >
