At 09:16 PM 9/29/2010, Suraj Gowda wrote:
At 3 Gs/s, the FPGA clock rate is 187.5 MHz. Is this in range of the
DRAM clock?
Maybe you could describe what the output is and/or how it's incorrect?
It's been a while since I attempted to use that interface.
We had a 200 MHz sine wave input to the ADC and the first 8 ADC
outputs seemed to provide reasonable data, while the second set of 8
ADC outputs were always a value of 128.
Since this didn't seem to be working, we wanted to try it with 8
simultaneous outputs which I believe requires the FPGA clock to run
at 375 MHz, correct? That's when we found that the DRAM couldn't run
this fast, hence John's original question.
187.5 MHz would be the clock rate with the ADC set to provide 16
simultaneous outputs, correct?
Thanks,
Jason
_Suraj
On Sep 29, 2010, at 6:08 PM, John Ford wrote:
Hi John,
Just to clarify, do you mean 1 board with 16 outputs / cycle at half
the clock rate? I implemented this feature but I wouldn't recommend
using it for serious computation. For operations like FFT, speed is
not as much a problem as the number of simultaneous
Yes, that's what I meant. We're trying to test the board at 3 GS/s by
collecting a long snapshot into DRAM, which doesn't run at 375 MHz,
so we
thought we'd just run it at the 2x demux into the dram interface.
We can run the board at 1.5 GS/s with 8 outputs, but when we try the
16
output mode at 3 GS/s it doesn't seem to work right.
So you would run the board at twice the clock rate and demux the
output
samples on the FPGA in the simulink model before writing into dram?
Thanks for the info!
John
-Suraj
On Sep 29, 2010, at 5:51 PM, John Ford wrote:
Hi all.
Does anyone have a working example of using the adc083000 adc board
in the
2* demultiplexed mode (16 simultaneous outputs).
If so, what sampling rate?
Thanks!
John
