Andrea Mattana wrote: > Guy Kenfak wrote: >> I got this message, >> >> To disable the PAR timing check: >> >> 1> Disable the "Treat timing closure failure as error" >> option from the Project Options dialog in XPS. >> >> OR >> >> 2> Type following at the XPS prompt: >> XPS% xset enable_par_timing_error 0 > > I got many times this error. It seems that is rather hard to > understand where is the problem, I have solved by adding delays > somewhere on the design. > > How we can track it on the design in order to fix the timing > contraints? In the timing report there is no indication on which > block do not meet timing constraints...
As David mentioned, all the information you need to track down timing errors is in the timing report. Rather than reading system.twr, you might find it easier to open system.twx with Timing Analyzer. > Are we sure that disabling this check (if possible using simulink) > do not affect the project behaviour? When you generate bitstreams for designs that failed to meet timing, you can never be sure of what will happen. Sometimes the fpga will program successfully, but you won't be able to write to registers. Sometimes you'll try to program the fpga, and the board will become unresponsive and require a hard reset. Sometimes, things will seem to work -- but this is pretty rare. There are probably other modes of failure that i've not yet encountered. There is no way to predict the behavior of a design if it fails to meet timing. So, you really don't want to disable that check. Billy
