Hi everyone,
I could sucessfully synthesize the spectrometer example, now I tried to
change input frequency from the original 800MHz to 2000MHz using
interleave mode, in order to avoid major changes in the design, I
connected o0, o2, o4 and o6 in the pfb block (putting a terminator on
the rest on the ADC outputs), after some minutes compiling a timing
error appears, very similar that I had before but because of a low freq
input clock, this time I'm trying to work with a higher value than
design, the error is as follow:
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case
| Best Case | Timing | Timing
| | Slack
| Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* PERIOD analysis for net "spec_2ghz_adc/sp | SETUP |
-0.618ns| 2.618ns| 1949| 324926
ec_2ghz_adc/adc_clk_dcm" derived from NE | HOLD |
-0.179ns| | 2718| 251622
T "spec_2ghz_adc/spec_2ghz_adc/adc_clk_bu | MINPERIOD |
-0.222ns| 2.222ns| 393| 87245
f" PERIOD = 2 ns HIGH 50% duty cycle cor | MINLOWPULSE |
0.000ns| 2.000ns| 0| 0
rected to 2 nS HIGH 1000 pS | MINHIGHPULSE|
0.000ns| 2.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
* NET "spec_2ghz_adc/spec_2ghz_adc/adc_clk_ | MINPERIOD |
-0.221ns| 2.221ns| 1| 221
buf" PERIOD = 2 ns HIGH 50% | |
| | |
----------------------------------------------------------------------------------------------------------
This same adc_clk_buf and adc_clk_dcm gave me some headaches before
with low clock frequency, but that time David George advice me to change
in
xps_lib/XPS_ROACH_base/pcores/adc_interface_v1_01_a/hdl/vhdl/adc_interface.vhd
variables FS_FREQUENCY_MODE and DLL_FREQUENCY_MODE from HIGH to LOW.
Now those variables are set in HIGH, so how can I make ADC/ROACH happy
with this 2GHz input clock?
Cheers,
Daniel H.
