Hey Daniel
Things start to get sticky when you go above 200MHz FPGA clock with that
tute 3 spectrometer, so you might have to tweak some things under the
hood to get it working at 250MHz. Have a look at this thread:
http://www.mail-archive.com/[email protected]/msg01804.html
As Mark said, have a look at the detailed timing report to try and track
down the rogue blocks.
Also, make sure you're using an up-to-date git repository; Andrew made
some useful changes to the pfb and adc blocks to make them behave nicer
at higher frequencies (thanks Andrew!). In particular, these commits are
a must:
http://casper.berkeley.edu/git/?p=mlib_devel/bwrc.git;a=commit;h=d81d7523efbbb7668ea04a4b3ce3ddc3107ad875
http://casper.berkeley.edu/git/?p=mlib_devel/bwrc.git;a=commit;h=37c90e2b98da3a48a4d3f7b67980fdd28b32a6ce
To summarize all this, to get the spectrometer working at 250MHz I would
suggest:
* updating to the latest git repository
* deleting the PFB_FIR_REAL block and dragging in a new one from your
newly updated library
* deleting the FFT block too, and adding in a new one
* changing to the settings mentioned here:
http://www.mail-archive.com/[email protected]/msg01804.html
Hope that makes sense!
Cheers and good luck
Danny
On 01/03/2011 22:17, Mark Wagner wrote:
Hi Daniel,
From the Matlab command prompt, you can type dos('timingan') and then
open the timing report ./XPS_ROACH_base/implementation/system.twx from
the analyzer. You'll see where the timing issues are occurring (i.e.
negative slack). You can then go back to your design and add
registers or delays where appropriate to hopefully allow data to
propagate in a reasonable time. This takes up resources though, and
can sometimes make things worse. If you're unable to get the design
to meet timing at this point, it may behoove you to use the floor
planner.
Mark
2011/3/1 Daniel Esteban Herrera Peña <[email protected]
<mailto:[email protected]>>
Continuing with the frequency problem...
Now from CentOS I checked the same design, it's the spectrometer
from tutorial 3 which I change freq from 800 to 1000MHz and I also
change the User IP Clock Rate from 200 to 250MHz, the synthesis
stops in the same error, but now I see that the numbers are slight
different:
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst
Case | Best Case | Timing | Timing
| |
Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* PERIOD analysis for net "tut3_adc/tut3_ad | SETUP |
-1.638ns| 5.638ns| 110| 45473
c/adc_clk_dcm" derived from NET "tut3_ad | HOLD |
0.102ns| | 0| 0
c/tut3_adc/adc_clk_buf" PERIOD = 4 ns HIG | |
| | |
H 50% | |
| | |
I don't know what else I need to do! any insight will be greatly
appreciated!
Cheers,
Daniel.
On Fri, 25 Feb 2011 16:46:45 -0300, Daniel Esteban Herrera Peña
<[email protected] <mailto:[email protected]>> wrote:
Hi Henry,
Thanks for your quick response, as you thought, I indeed enter
2000... in the meantime I digest how ADC works, I tried to compile
changing freq 800 to 1000 in the original design (no
interleaving),
and I receive this error:
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst
Case | Best Case | Timing | Timing
| |
Slack
| Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* PERIOD analysis for net "spec_1ghz_adc/sp | SETUP |
-0.656ns| 4.656ns| 123| 31325
ec_1ghz_adc/adc_clk_dcm" derived from NE | HOLD |
0.118ns| | 0| 0
T "spec_1ghz_adc/spec_1ghz_adc/adc_clk_bu | |
| | |
f" PERIOD = 4 ns HIGH 50% | |
| | |
----------------------------------------------------------------------------------------------------------
TS_epb_clk = PERIOD TIMEGRP "epb_clk" 88 | SETUP |
0.134ns| 11.229ns| 0| 0
MHz HIGH 50% | HOLD |
0.360ns| | 0| 0
----------------------------------------------------------------------------------------------------------
NET "spec_1ghz_adc/spec_1ghz_adc/adc_clk_ | MINLOWPULSE |
1.000ns| 3.000ns| 0| 0
buf" PERIOD = 4 ns HIGH 50% | |
| | |
----------------------------------------------------------------------------------------------------------
NET "epb_cs_n_IBUF" MAXDELAY = 4 ns | MAXDELAY |
2.366ns| 1.634ns| 0| 0
----------------------------------------------------------------------------------------------------------
NET "spec_1ghz_adc/spec_1ghz_adc/adc_clk_ | N/A |
N/A| N/A| N/A| N/A
buf" PERIOD = 4 ns HIGH 50% | |
| | |
----------------------------------------------------------------------------------------------------------
I see with this that I won't even be able to compile an
interleaved
design, what else I can try?
Thank you,
Daniel H.
On Fri, 25 Feb 2011 10:58:47 -0800, Henry Chen
<[email protected] <mailto:[email protected]>>
wrote:
Hi Daniel,
It looks like you might have put 2000 into the "ADC clock
rate"
setting in the ADC yellow block. This will try to run the
FPGA at
500MHz, which explains the timing error (it's very difficult
to run the FPGA beyond 350MHz for a complex DSP design).
I'm guessing you want to sample at 2GS/s, in which case
you would put
1000 into the "ADC clock rate" box, and check the "ADC
interleave mode"
box, which will give you the effective 2GHz sampling rate.
It will also
run the FPGA at a much more manageable 250MHz.
What you put into the "ADC clock rate" box indicates the
frequency of
the actual sampling clock signal you would connect to the
ADC board,
rather than the effective sampling rate. For the iADC it
can't go much
beyond 1GHz.
Sorry that it's kind of confusing!
Thanks,
Henry
On 2/25/2011 7:56 AM, Daniel Esteban Herrera Peña wrote:
Hi everyone,
I could sucessfully synthesize the spectrometer
example, now I tried to change input frequency from
the original 800MHz to 2000MHz using interleave mode,
in order to avoid major changes in the design, I
connected o0, o2, o4 and o6 in the pfb block (putting
a terminator on the rest on the ADC outputs), after
some minutes compiling a timing error appears, very
similar that I had before but because of a low freq
input clock, this time I'm trying to work with a
higher value than design, the error is as follow:
Asterisk (*) preceding a constraint indicates it was
not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check
| Worst Case | Best Case | Timing | Timing
|
| Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* PERIOD analysis for net "spec_2ghz_adc/sp | SETUP
| -0.618ns| 2.618ns| 1949| 324926
ec_2ghz_adc/adc_clk_dcm" derived from NE | HOLD
| -0.179ns| | 2718| 251622
T "spec_2ghz_adc/spec_2ghz_adc/adc_clk_bu | MINPERIOD
| -0.222ns| 2.222ns| 393| 87245
f" PERIOD = 2 ns HIGH 50% duty cycle cor |
MINLOWPULSE | 0.000ns| 2.000ns| 0|
0
rected to 2 nS HIGH 1000 pS |
MINHIGHPULSE| 0.000ns| 2.000ns| 0|
0
----------------------------------------------------------------------------------------------------------
* NET "spec_2ghz_adc/spec_2ghz_adc/adc_clk_ |
MINPERIOD | -0.221ns| 2.221ns| 1|
221
buf" PERIOD = 2 ns HIGH 50% |
| | | |
----------------------------------------------------------------------------------------------------------
This same adc_clk_buf and adc_clk_dcm gave me some
headaches before with low clock frequency, but that
time David George advice me to change in
xps_lib/XPS_ROACH_base/pcores/adc_interface_v1_01_a/hdl/vhdl/adc_interface.vhd
variables FS_FREQUENCY_MODE and DLL_FREQUENCY_MODE
from HIGH to LOW. Now those variables are set in HIGH,
so how can I make ADC/ROACH happy with this 2GHz input
clock?
Cheers,
Daniel H.
--
--------------------------------
Daniel Esteban Herrera Peña
Ingeniero Civil Electrónico
Universidad de Concepción, Chile.
(41)236-0289 842-38325
--------------------------------
