Martin, Thanks for your reply. Please see below.
On 01/03/2011 4:32 AM, Andrew Martens wrote:
Hi Mandana
On 1 March 2011 02:59, Mandana Amiri <[email protected]
<mailto:[email protected]>> wrote:
Hi everyone,
I download poco (tut4) on my Roach board and supply -10dbm 250MHz
signals and when I read back the value of the status register, I
have x 000f0f00, which means fft_over and eq_clip are set. I tried
changing the quant0_gain, etc values hoping that eq_clip would be
cleared, but it did not not change.
From the looks of it, the fft and equaliser are clipping, but not the
ADC inputs.
Have you written anything into the fft_shift register? If you have
not, then overflow
will occur in the FFT (and likely in the equaliser). This is
especially true with a
sinusoidal input, where the FFT will add a gain of logn/2 (n = FFT
size) to that
channel. Try writing 0x7FF to fft_shift to enable shifting on every
stage, this
should solve your problem
fft_shift is set to 0xffffffff by default in tutorial 4 poco design.
Any other suggestions?
When I monitor my ADC input levels, they are about 4.6 bit used.
My next question is what is the dip that I see in the middle of
the auto- and cross-correlation plots, regardless of signals
applied or just terminated inputs.
Not so sure about this, possibly include a plot if you can.
Please see the attached plot. I have a Roach board and 2 x 1GS/s ADC
boards. In this plot, a 500MHz sine is connected to the first input
(channel a), while the other 3 inputs are terminated (channels b, c, d)
and an 800MHz clock is supplied. What is the small dip in the centre
(@channel 500). This is also present in the plot posted on page 15 of
casper_workshop_tut4.pdf.
m
Thanks,
Mandana
Regards
Andrew
