UPDATE:
I created new netlists and verilog files of {fab,cpu}_op_fifo and
rx_fifo, using FIFO Generator v4.3 and selecting the options according
to the original XCO files.
The only thing that I did not copy exactly is the reset_type option of
the rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this
error from xst:
...
INSTANCE:iic_adc0...
ERROR:HDLCompilers:91 ...
\kat_adc_iic_controller_v1_00_a/hdl/verilog/kat_adc_iic_controller.v"
line 125 Module 'rx_fifo' does not have a port named 'rst'
...
The thing is that sync. reset rename the pin to "srst" instead "rst".
For testing purposes, I changed this option to async:
reset_type=Asynchronous_Reset, and the synthesis finished!! But, is this
a safe procedure?
I programmed a Roach board, but I am not sure if this trick worked?
--------------------------
In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')
Out[41]: 'ok'
In [36]: corr.katadc.get_ambient_temp(fpga,0)
Out[36]: 0.0
In [37]: corr.katadc.eeprom_details_get(fpga,0)
Out[37]:
{'adc_ic_id': 0,
'pcb_rev': 0,
'reserved': (0, 0, 0, 0),
'rf_fe_id': 0,
'serial_number': 0}
--------------------------
How can I test if this is working?
Thanks again,
-- Luis Quintero, Arecibo Observatory
On 03/25/2011 04:57 PM, Luis Quintero wrote:
Dear katADC users,
I am trying to synthesize a simple design using the katadc block (see
screen capture in the attachments). This is my tool set in a Windows
XP machine: ISE 10.1, SysGen v.10.1.1134, MATLAB R2007b, v7.5.0.342,
latest CASPER libs (today's git clone
http://casper.berkeley.edu/git/mlib_devel.git).
I am getting an exception in xst for iic_adc0:
...
EXCEPTION:Xdm:FileReader.c:428:$Id: FileReader.c,v 1.36 2004/09/15
20:29:16 jdl Exp $ - Xdm_Exception::UnsupportedFileFormatVersion The
Xdm_Model File Format version 'V1.5e' is not supported.
...
The explanation of this issue is available in the Xilinx answers
database AR#33915 (http://www.xilinx.com/support/answers/33915.htm).
This problem is caused for version incompatibility of the software
that generates some netlist of the CASPER libs and my toolset version.
I tried to find all the "iic" things related to katadc in the libs,
and generate the netlist using my Xilinx core generator. I started
with kat_iic_controller_v1_00_a, I generated the {op,rx}_fifo modules,
and I am getting the same exception error from xst.
Then I moved to kat_adc_iic_controller_v1_00_a with not success.
Apparently the coregen project uses the FIFO generator v5.3, the
latest version that I have is v.4.3.
So, my questions are:
- Am I seeing the problem in the right way?
- Can I generate the netlists of {fab,cpu}_op_fifo and rx_fifo using
v4.3 and synthesize the design? If so, can I use the same parameters
of the XCO files?
- Do I have to migrate to ISE/SysGen ver. > 11.x? (I planning to do
this in the future...)
Thanks!
-- Luis Quintero, Arecibo Observatory
