Hi Luis.
> I created new netlists and verilog files of {fab,cpu}_op_fifo and rx_fifo,
> using FIFO Generator v4.3 and selecting the options according to the original
> XCO files.
As you have worked out, the FIFO netlists were generated using ISE 11
tools, making them incompatible with 10.1. Regenerating them as you
did was the right way to go. There shouldn't be any reason that you
cant use the KATADC with 10.1.
>
>
> The only thing that I did not copy exactly is the reset_type option of the
> rx_fifo in v5.3: reset_type=Synchronous_Reset. I am getting this error from
> xst:
>
This shouldn't make any difference. Synchronous resets are probably best anyway.
>
> I programmed a Roach board, but I am not sure if this trick worked?
>
> --------------------------
> In [41]: fpga.progdev('katadc_alone_2011_Mar_25_1844.bof')
> Out[41]: 'ok'
>
> In [36]: corr.katadc.get_ambient_temp(fpga,0)
> Out[36]: 0.0
>
> In [37]: corr.katadc.eeprom_details_get(fpga,0)
> Out[37]:
> {'adc_ic_id': 0,
> 'pcb_rev': 0,
> 'reserved': (0, 0, 0, 0),
> 'rf_fe_id': 0,
> 'serial_number': 0}
> --------------------------
>
This is definitely not working. I suspect you are getting all zero's
on reads. I'm not really sure why this is happening.
Firstly I would check that PPC comms are okay by reading and writing
to the sys_scratchpad register. I would then dump the
kat_iic_controller register and look for any non-zero values. If you
don't see anything this most likely means something is wrong with the
generated EDK project. Exactly, what would be hard to say. You could
post your generated XPS_ROACH_base/system.mhs and coreinfo.tab files
which may give some clues.
I think Jason might have some code which manipulates the
kat_iic_controller register directly. This might provide a little more
insight than the corr routines.
Hopefully we can work this one out quickly.
Cheers,
David
