Hi Miguel, I think the "General ROACH Instructions" that you're reading were written specifically for the CASPER workshop in Harvard last year, where there were some servers / ROACHs already set up. If you're trying to run your design on a ROACH in your own setup, a few of the details may be slightly different. In particular, you can ignore the "Using VNC to connect to the servers" section, since it refers to using remote servers for designing with Simulink. The rest of the document should still be relevant, but details specific to particular computers used at the workshop (e.g. "paper2") will not be the same in your set up.
To transfer the design to ROACH, all you need to do is copy (using SCP on linux or winSCP on windows) the .bof which is generated after compilation to a location where it is accessible by the ROACH. The .bof file lives in the bit_files subdirectory of your compile path, and has a name of the form <model_name>_<compile time & date>.bof. Each time you compile your design, a new bof file with a new timestamp should appear in this directory. Where you need to copy the boffile depends a little on your ROACH setup. If you are booting the ROACH from an SD card you can send the boffile straight to the boffiles directory (/boffiles) on your ROACH. If you are booting your ROACH from a filesystem hosted on a server, you should copy your boffile to this server, placing it in the boffiles directory of wherever your ROACH filesystem lives. For example, for our setup in Oxford (where be boot via NFS), boffiles are copied to /srv/roachfs/fs/boffiles/ on our server "caezar". If your ROACHs are not yet set up, I would suggest going down the NFS route, which requires a little bit of installing and configuring of linux packages on a server, but once set up is (at least in my experience) pretty trouble free, and much more convenient when you have multiple ROACH boards. Instructions for setting up NFS on an Ubuntu machine are available here -- http://casper.berkeley.edu/wiki/ROACH_NFS_guide You may also find this document, particularly the NFS section, useful -- http://casper.berkeley.edu/wiki/Getting_Started_with_ROACH Cheers, Jack On 7 April 2011 11:15, <[email protected]> wrote: > Hi, > > Now i'm ready to transfer tut1 to the FPGA. > On General Roach Instructions it said i need a VNC session to the servers. > How can i get it? > > Cheers, > Miguel. > > > -----Mensaje original----- From: John Ford > Sent: Wednesday, April 06, 2011 5:49 PM > To: [email protected] > Cc: [email protected] > Subject: Re: [casper] Roach: Getting Started Enviroment 2011 > > Hi John, >> >>> >>> 4) It's better but i still get an error. After 2 hours and a half I get >>> the >>> following error. Must i follow the instructions and it doesn't matter?: >>> >> >> Unfortunately this error is real. Ignoring timing errors is not a good >> idea in general. Is this on a tutorial that's known to build? If it's on >> your own design, you'll need to modify it or simplify it in some way. >> Maybe fewer taps in the PFB, or fewer channels in the FFT? >> >> No is not my own design. I was trying to run Roach tutorial 3 downloaded >> from Casper web site >> ( >> http://casper.berkeley.edu/svn/trunk/ref_designs_tutorials/workshop_2010/roach_tut3_wideband_spec/ >> ). >> I was trying to run the tutorials before running my own design just to be >> sure about my configuration. >> >> So.. do i have to modify the original model? >> > > Hmm. > > I would have thought the tutorial would successfully compile without you > having to modify it. We don't have a working 10.1 installation at > present, so I can't try it on that. Have you got the latest update of > 10.1 from xilinx? That might make a difference. > > As a test, try reducing the number of channels in the FFT and compile it > again to see if it can route that successfully. > > John > > >> >> -----Mensaje original----- >> From: John Ford >> Sent: Wednesday, April 06, 2011 2:58 PM >> To: [email protected] >> Cc: [email protected] >> Subject: Re: [casper] Roach: Getting Started Enviroment 2011 >> >> Wow! Thank you for your replies! >>> >>> Ok let's see: >>> >>> 1) It was solved with Mark instructions >>> >>> 2) It's solved following Zhu instructions >>> >>> 3) It's also ok by replacing the block as you suggested me. >>> >> >> Excellent! >> >> >>> 4) It's better but i still get an error. After 2 hours and a half I get >>> the >>> following error. Must i follow the instructions and it doesn't matter?: >>> >> >> Unfortunately this error is real. Ignoring timing errors is not a good >> idea in general. Is this on a tutorial that's known to build? If it's on >> your own design, you'll need to modify it or simplify it in some way. >> Maybe fewer taps in the PFB, or fewer channels in the FFT? >> >> It's interesting and helpful to use the timing analyzer to show the paths >> that don't meet timing. Then you can adjust latencies and add delays to >> compensate sometimes. You might gain timing margin by inserting delay >> blocks (registers) in the wires from the ADC to the rest of the system, or >> wherever the timing analyzer shows the problem. >> >> John >> >> >>> >>> #----------------------------------------------# >>> # Starting program post_par_trce >>> # trce -e 200 -xml system.twx system.ncd system.pcf >>> #----------------------------------------------# >>> Release 10.1.03 - Trace (nt) >>> Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. >>> >>> >>> Loading device for application Rf_Device from file '5vsx95t.nph' in >>> environment >>> c:\Xilinx\10.1\ISE. >>> "system" is an NCD, version 3.2, device xc5vsx95t, package ff1136, >>> speed -1 >>> WARNING:ConstraintSystem:65 - Constraint <NET >>> "r_spec_2048_r105_adc/r_spec_2048_r105_adc/adc_clk_buf" PERIOD = 5 ns >>> HIGH >>> 50%;> [system.pcf(39150)] overrides constraint <NET >>> "r_spec_2048_r105_adc/r_spec_2048_r105_adc/adc_clk_buf" PERIOD = 5 ns >>> HIGH >>> 50%;> [system.pcf(39148)]. >>> >>> INFO:Timing:3377 - Intersecting Constraints found and resolved. For >>> more >>> information see the TSI report. >>> >>> -------------------------------------------------------------------------------- >>> Release 10.1.03 Trace (nt) >>> Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. >>> >>> trce -e 200 -xml system.twx system.ncd system.pcf >>> >>> >>> Design file: system.ncd >>> Physical constraint file: system.pcf >>> Device,speed: xc5vsx95t,-1 (PRODUCTION 1.64 2008-12-19, >>> STEPPING >>> level 0) >>> Report level: error report, limited to 200 items per >>> constraint >>> >>> -------------------------------------------------------------------------------- >>> >>> INFO:Timing:2752 - To get complete path coverage, use the unconstrained >>> paths >>> option. All paths that are not constrained will be reported in the >>> unconstrained paths section(s) of the report. >>> INFO:Timing:3339 - The clock-to-out numbers in this timing report are >>> based >>> on a >>> 50 Ohm transmission line loading model. For the details of this >>> model, >>> and >>> for more information on accounting for different loading conditions, >>> please >>> see the device datasheet. >>> >>> >>> Timing summary: >>> --------------- >>> >>> Timing errors: 34 Score: 3676 >>> >>> Constraints cover 279937 paths, 1 nets, and 50172 connections >>> >>> Design statistics: >>> Minimum period: 11.245ns (Maximum frequency: 88.928MHz) >>> Maximum net delay: 1.637ns >>> >>> >>> Analysis completed Tue Apr 05 17:11:06 2011 >>> >>> -------------------------------------------------------------------------------- >>> >>> Generating Report ... >>> >>> Number of warnings: 1 >>> Number of info messages: 3 >>> Total time: 1 mins 10 secs >>> >>> >>> xflow done! >>> touch __xps/system_routed >>> xilperl C:/Xilinx/10.1/EDK/data/fpga_impl/observe_par.pl -error yes >>> implementation/system.par >>> Analyzing implementation/system.par >>> >>> ******************************************************************************** >>> ERROR: 1 constraint not met. >>> >>> PAR could not meet all timing constraints. A bitstream will not be >>> generated. >>> >>> To disable the PAR timing check: >>> >>> 1> Disable the "Treat timing closure failure as error" option from the >>> Project Options dialog in XPS. >>> >>> OR >>> >>> 2> Type following at the XPS prompt: >>> XPS% xset enable_par_timing_error 0 >>> >>> ******************************************************************************** >>> make: *** [implementation/system.bit] Error 1 >>> ERROR:MDT - Error while running "make -f system.make bits" >>> No changes to be saved in MSS file >>> Saved project XMP file >>> Error using ==> gen_xps_files at 680 >>> Programation files generation failed, EDK compilation probably also >>> failed. >>> >>> >>> >>> >>> >>> >>> -----Mensaje original----- >>> From: John Ford >>> Sent: Tuesday, April 05, 2011 3:32 PM >>> To: Zhu, Yan >>> Cc: [email protected] ; [email protected] >>> Subject: Re: [casper] Roach: Getting Started Enviroment 2011 >>> >>> Hi Miguel, >>>> >>>> For 2, put load_system('xps_library'), load_system('casper_library') >>>> and >>>> load_system('gavrt_library') into your startup.m may solve this issue. >>>> It is due to the libraries are not initialized properly. >>>> >>> >>> Also, note that the "Parameterized link" warning is normal, and does not >>> cause trouble. It's due to the library blocks disconnecting from the >>> library when they redraw, if I remember right. >>> >>> You can/should ignore them. >>> >>> John >>> >>> >>> >>> >>>> For 3, the posedge block has been changed from 'Misc/pulse_ext/posedge' >>>> to 'Misc/posedge' in casper_library, up one level. Just replace it with >>>> a new one inside 'pkt_sim' block. >>>> >>>> For 4, I'm not sure but could you please try if this 'clock pin' trick >>>> helps? see: >>>> http://www.mail-archive.com/[email protected]/msg01070.html for >>>> detail. >>>> It is mentioned at the last section of >>>> http://casper.berkeley.edu/wiki/Xilinx_ISE_11.4_Setup >>>> >>>> For casper tools running environment, we use below combination >>>> >>>> CentOS 5.5 x86_64 >>>> Matlab 2009b >>>> Xilinx ISE 11.5 >>>> >>>> If you need to run python client scripts on CentOS 5.5, you must >>>> install >>>> a separate python 2.6 from EPEL repository and manually compile numpy, >>>> matplotlib, ipython, katcp, corr etc. >>>> >>>> >>>> Zhu Yan >>>> >>>> >>>> >>>> On 4/5/2011 5:58 PM, Mark Wagner wrote: >>>> >>>>> Hi Miguel, >>>>> >>>>> For 2, try opening a new model file and putting in the XSG_core_config >>>>> and System Generator blocks, pulling them from their libraries. Then >>>>> open up tut1 and copy everything except the XSG_core_config and the SG >>>>> blocks and paste it into your new model file. Save and ctrl-D. If >>>>> that >>>>> doesn't work, you may have to redraw tut1 from scratch. >>>>> >>>>> Mark >>>>> >>>>> >>>>> On Tue, Apr 5, 2011 at 3:54 AM, ---> Miguel A. S. G <--- >>>>> <[email protected] <mailto:[email protected]>> wrote: >>>>> >>>>> Hi Mark, >>>>> Thank you for your quick reply. Following your instructions... >>>>> 1.- It's solved. >>>>> 2.- It's not solved. I mean, I swapped the blocks of tut1.mdl with >>>>> blocks from my library. Save the model, close matlab, open matlab >>>>> and same "bad links" appear. >>>>> 3 and 4.- Im not at work now so.. tomorrow i will try it. >>>>> Thank you anyway! >>>>> Miguel. >>>>> >>>>> *From:* Mark Wagner <mailto:[email protected]> >>>>> *Sent:* Monday, April 04, 2011 9:05 PM >>>>> *To:* [email protected] <mailto:[email protected]> >>>>> *Cc:* [email protected] <mailto:[email protected]> >>>>> *Subject:* Re: [casper] Roach: Getting Started Enviroment 2011 >>>>> >>>>> Hi Miguel, >>>>> >>>>> Sorry you're having so much trouble. >>>>> >>>>> 1. This is just a warning you're getting and doesn't hav any >>>>> effect >>>>> on the functionality of the toolflow, but you can comment out: >>>>> >>>>> Browser(2).Library = 'testbench_lib'; >>>>> Browser(2).Name = 'Testbench Blockset'; >>>>> >>>>> in mlib_devel/gavrt_library/slblocks.m, and you should stop >>>>> getting >>>>> that warning. >>>>> >>>>> 2. I think this is because you are opening up the model file with >>>>> a >>>>> newer library than what it was originally created with. But I >>>>> think >>>>> you solved this already by deleting the block and pulling from the >>>>> library you're opening the model file with. >>>>> >>>>> 3. If you look at this posedge, I think it's not being loaded >>>>> correctly. If you try deleteing and replacing the posedge >>>>> (tut2/pkt_sim/posedge) like you did in 2, it should fix the >>>>> problem. >>>>> >>>>> 4. I'm not sure what the issue is here, but try ctrl-D, which will >>>>> update the design and propagate the data types and hopefully it >>>>> will >>>>> give a more telling error. >>>>> >>>>> Best, >>>>> Mark >>>>> >>>>> >>>>> On Tue, Apr 5, 2011 at 1:43 AM, <[email protected] >>>>> <mailto:[email protected]>> wrote: >>>>> >>>>> Hi Griffin, >>>>> Thank you so much!! >>>>> About the first option >>>>> centos 5.3 / Xilinx ISE 11.4 / Matlab 2009b >>>>> Are Casper Libraries compatibles with? I mean, don’t >>>>> are >>>>> they >>>>> build for Ise 10.1? >>>>> My problems? Ok let’s go step by step: >>>>> 1) Each time I open simulink: >>>>> Warning: Could not find library ‘testbench_lib’ o >>>>> speciefied in >>>>> ‘C:\codigos\mlib_devel\gavrt_library\slblocks.m’ >>>>> 2) The first time i open a model all the yellow blocks are >>>>> “bad >>>>> link†and matlab welcomes me with a lot of warnigs like: >>>>> “Warning: "tut1/counter_value" is a parameterized link. >>>>> To >>>>> view, >>>>> discard, or propagate the changes for this link, >>>>> use the "Link Options" menu item.†With the >>>>> tutorial 2 I also get four warnings like, >>>>> “Warning: casper_library_misc.mdl, line 5905: >>>>> block_diagram >>>>> does >>>>> not have a parameter named 'BlockName'†. >>>>> And others warning about a parameter "SID†(I can >>>>> remember a >>>>> discussion about SID in the casper list) >>>>> Anyway, then I pick up an element from BEE_XPS System Blockset >>>>> (i can see this library in the simulink library browser) , put >>>>> it in the model and the yellow blocks became ok. >>>>> 3) When I tried to run ‘bee_xps’ with >>>>> ‘tut2.mdl’ i get >>>>> the same >>>>> warnings plus the following error: >>>>> Error using ==> gen_xps_files at 199 >>>>> Failed to find 'Misc/pulse_ext/posedge' in library >>>>> 'casper_library' referenced by 'tut2/pkt_sim/posedge'. >>>>> 4) With tutorial3 after “bee_xps†the thing are >>>>> getting >>>>> worse... >>>>> I received around fifty errors like (i only copy two of them >>>>> but >>>>> i have a .txt file if someone is interested in): >>>>> “Error using ==> gen_xps_files at 199 >>>>> --> Error reported by S-function 'sysgen' in >>>>> 'r_spec_2048_r105/Concat1': >>>>> An internal error occurred in the Xilinx Blockset Library. >>>>> Please report this error to Xilinx >>>>> (http://support.xilinx.com), >>>>> in as much detail as possible. You may also find immediate >>>>> help >>>>> in the Answers Database and other online resources at >>>>> http://support.xilinx.com. >>>>> Since it is possible that this internal error resulted from an >>>>> unhandled usage error in your design, we advise you to >>>>> carefully >>>>> check the usage of the block reporting the internal error. If >>>>> errors persist, we recommend that you restart MATLAB.†>>>>> “--> Error in 'r_spec_2048_r105/sync_cnt': >>>>> Initialization >>>>> commands cannot be evaluated. MATLAB error message: Error >>>>> using >>>>> ==> register_mask at 48 >>>>> Error evaluating 'MoveFcn' callback of Xilinx Gateway Out >>>>> Block >>>>> block (mask) >>>>> >>>>> 'r_spec_2048_r105/sync_cnt/r_spec_2048_r105_sync_cnt_user_data_in'. >>>>> Error using ==> xlBlockMoveCallback at 53 >>>>> Error reported by S-function 'sysgen' in >>>>> >>>>> 'r_spec_2048_r105/sync_cnt/r_spec_2048_r105_sync_cnt_user_data_in': >>>>> An internal error occurred in the Xilinx Blockset Library. >>>>> Please report this error to Xilinx >>>>> (http://support.xilinx.com), >>>>> in as much detail as possible. You may also find immediate >>>>> help >>>>> in the Answers Database and other online resources at >>>>> http://support.xilinx.com. >>>>> Since it is possible that this internal error resulted from an >>>>> unhandled usage error in your design, we advise you to >>>>> carefully >>>>> check the usage of the block reporting the internal error. If >>>>> errors persist, we recommend that you restart MATLAB.†>>>>> I download the models from Casper web so i assume they will be >>>>> ok. This is the reason why i was wondering if i have the >>>>> correct >>>>> setup. I readed >>>>> http://www.xilinx.com/support/answers/17966.htm >>>>> and chose, Windows XP 32 bits, Matlab R2008a, ISE 10.1.3. >>>>> Theoretically... it should be valid but........ >>>>> Miguel. >>>>> ** >>>>> ** >>>>> *From:* Griffin Foster <mailto:[email protected]> >>>>> *Sent:* Monday, April 04, 2011 6:38 PM >>>>> *To:* [email protected] <mailto:[email protected]> >>>>> *Cc:* [email protected] >>>>> <mailto:[email protected]> >>>>> *Subject:* Re: [casper] Roach: Getting Started Enviroment 2011 >>>>> Hi Miguel, >>>>> >>>>> We are using a windows and linux setup which is: >>>>> >>>>> centos 5.3 / Xilinx ISE 11.4 / Matlab 2009b >>>>> windows XP / Xilinx ISE 10.1 / Matlab 2007b >>>>> >>>>> the main git repo is at: >>>>> git://casper.berkeley.edu/mlib_devel.git >>>>> <http://casper.berkeley.edu/mlib_devel.git> >>>>> >>>>> What kind of errors are you getting? >>>>> >>>>> -Griff >>>>> >>>>> On Mon, Apr 4, 2011 at 4:45 PM, <[email protected] >>>>> <mailto:[email protected]>> wrote: >>>>> >>>>> Hi all, >>>>> My name is Miguel. I started to work with Casper >>>>> enviroment >>>>> a couple of months ago. I’m trying to comunicate >>>>> severals >>>>> Roach through a swicth. >>>>> I readed on the web that the best choice was: Windows XP, >>>>> System Generator 10.1 and Matlab 2008a (as Xilinxs said, >>>>> it >>>>> was compatible) but i started to get (a lot of) warnings >>>>> and >>>>> errors. >>>>> I would like to be sure, because I still have a terrible >>>>> mess with Linux/Windows, Matlab, System generator versions >>>>> supported to work with Casper libraries, the respository >>>>> (isn’t a link to git repository on the web, is it?) >>>>> and >>>>> i’m >>>>> driving insane. >>>>> It would be very helpfull if someone could resume one/two >>>>> different options: >>>>> 1) Which O.S must I install? >>>>> 2) Which System Generator Version must i install? >>>>> 3) Which Matlab version must i use? >>>>> I mean, could anyone tell me for example : >>>>> “RED HAT 5, System Genereator 12.6, Matlab >>>>> 2011†or >>>>> “ubuntu 9.7, System Generator 10.1, Matlab >>>>> 2009a†they both work ok. >>>>> Thanks. >>>>> Miguel. >>>>> >>>>> >>>>> >>>>> >>>> >>>> >>> >>> >>> >> >> >> > > >
