That MKID ADC board has a maximum clock rate of 550MHz, so 1200 is not
going to work.
Rick
On 6/28/2011 6:39 AM, Jesús García wrote:
Hi,
I am trying to make a design with an ADC board and a DAC board working
with
different sampling rates, and up to date I have no success.
I am trying to do a simple design with the ADC using a sampling rate of
1200MHz and the DAC using a sampling rate of 150 MHz.
In the FPGA I simply implement a 8x down-sampling with a polyphase filter.
I have attached my system generator model, but the main blocks are
configured in this way:
XSG core config block:
-Hardware Platform Roach:Sx95t
-User Ip clock Source: Ac0_clk (because the ADC board is in the ZDOK0
connector)
-User Ip clock Rate:150 MHz
-Sample period 1
- Synthesis tool:XST
ADC mkid x4 block:
-ADC board:adc0
-ADC clock rate 1200 MHz
-ADC interleave mode checked
-Sample period 1
DAC mkid x4 block
-DAC board 1
-DAC clock 150 MHz
-Sample period 1
When I run the simulation with matlab everything is ok, but when I try to
generate the bof file I get time errors, because some constraints are not
met.
I think I need to modify the VHDL files of the DAC and ADC, to
generate the
proper clock signals....but I am not sure...so if anyone could help
me... I
would be very gratefull
Jesús
