hi jesus,
to follow up on rick and jack's comments:
to use the dual <=1Gsps ADC at 1200 Msps,
then as you point out, you need to use the
ADC in interleave mode:
you need to supply a 600 MHz clock to the ADC board;
and the ADC will then supply a 150 MHz clock
to the FPGA (the ADC clock is divided by four to drive
the FPGA clock), and the ADC yellow block will produce
8 ADC samples (64 bits) per FPGA clock.
best wishes,
dan
On 6/28/2011 3:21 PM, Jack Hickish wrote:
Hi Jesús,
If you're using the dac_4x block, which is designed for a DAC running
at 4x the "simulink clock", you're going to have problems if you want
to run both the FPGA and the DAC at 150MHz.
If you really want to do this, I guess you can make a new yellow block
(https://casper.berkeley.edu/wiki/How_to_make_a_%22yellow%22_block)
with the mutiplexing logic stripped out and different clock domain
crossing parameters. Check out the differences in the HDL for the two
DAC blocks which use different mux factors to shed some light on the
bits you'd need to change.
Of course, if you can get away with it, you could use the current
yellow block, clock the DAC at 150x4=600MHz, and just use each sample
4 times.
Cheers,
Jack
2011/6/28 Jesús García <[email protected]
<mailto:[email protected]>>
Hi,
I am trying to make a design with an ADC board and a DAC board
working with
different sampling rates, and up to date I have no success.
I am trying to do a simple design with the ADC using a sampling
rate of
1200MHz and the DAC using a sampling rate of 150 MHz.
In the FPGA I simply implement a 8x down-sampling with a polyphase
filter.
I have attached my system generator model, but the main blocks are
configured in this way:
XSG core config block:
-Hardware Platform Roach:Sx95t
-User Ip clock Source: Ac0_clk (because the ADC board is in the ZDOK0
connector)
-User Ip clock Rate:150 MHz
-Sample period 1
- Synthesis tool:XST
ADC mkid x4 block:
-ADC board:adc0
-ADC clock rate 1200 MHz
-ADC interleave mode checked
-Sample period 1
DAC mkid x4 block
-DAC board 1
-DAC clock 150 MHz
-Sample period 1
When I run the simulation with matlab everything is ok, but when I
try to
generate the bof file I get time errors, because some constraints
are not
met.
I think I need to modify the VHDL files of the DAC and ADC, to
generate the
proper clock signals....but I am not sure...so if anyone could
help me... I
would be very gratefull
Jesús
