Back when I had a bigger design built using 10.1 libraries, I was able to meet my timing constraits for a 1 GHz clock if I set the add delay value to 6. I had a comment that this was overkill, but it not only worked, but worked by an easy change in the mask instead of breaking this mask and putting multiple delays at various places within the FFT block, as someone else suggested. I am looking at the timing report in system.twr, but the complaints are about the adc clock, something which I had found is not the case but rather that unmet timing constraints along the line reflect badly back on the ADC.
I just tried again by not throwing the adders into the DSP48s and putting my timing settings just as I had when I did get a compile, and it failed. I think it's because I don't have these adders in the DPS48s. By the way, the design compiles and works at 800/200 MHz. Anyone got ideas, or an approach I can take towards meeting my constraints? thanks, Sam On Thu, Jul 28, 2011 at 6:27 PM, Suraj Gowda <[email protected]> wrote: > Using DSP48s with for addition with a latency of 2 yields the best timing > performance, from experience and Xilinx's recommendations, which is why it's > hard-coded. > -Suraj > > On Thu, Jul 28, 2011 at 11:53 AM, Samuel Tun <[email protected]> wrote: >> >> Yes, unchecking the DSP48 adders allows me to change the add latency. >> I had that option selected because it was one of the recommendations >> towards meeting time constraints. I will test this out now and see. >> Thanks for your help. >> >> -Sam >> >> >> On Thu, Jul 28, 2011 at 12:32 PM, Hong Chen <[email protected]> >> wrote: >> > Hi Sam, >> > Did you activate the 'DSP48 adders in butterfly' option in the >> > Implementation section? The add delay value will be fixed to 2 when that >> > option is on. Would you mind try turn off that and see if it works? >> > Thanks, >> > -Hong >> > >> > On Thu, Jul 28, 2011 at 9:24 AM, Samuel Tun <[email protected]> >> > wrote: >> >> >> >> Hi, >> >> >> >> I am using the latest BWRC libraries in Linux, and I found that I >> >> cannot change the add delay values in the FFT block mask. Back when I >> >> was using the 10.1 libraries, changing this delay value along with >> >> other parameters along the PFB chain allowed me to meet timing >> >> constraints for a 1 GHz clock without having to break masks and >> >> putting multiple fixes all over the place. Does anyone know if this is >> >> just happening to me, or if it was hardcoded, and most importantly, >> >> how can I change this value? >> >> >> >> thanks ya'll, >> >> Sam Tun >> >> >> > >> > >> > >
