Hi Glenn,
I came across a similar issue while porting the ASIAA 5GSps ADC to
ROACH2, and also directly instantiated an MMCM in the pcore. I didn't
think to support lower FPGA clock rates but I think it's a really good
idea.
Perhaps the quickest way (without editing any HDL) is to have two
separate pcores, one for higher rates and one for lower rates, and
dynamically choose which core you want by setting the XPS block's
'ip_name' field to the appropriate pcore. Our 5GSps block does this to
choose between board versions.
A better way, I think, would be to add a new parameter to the Verilog
interface (that gets passed down to the MMCM) and set it using
conditional statements within the MHS file. Again, our block does this
for setting various parameters shared between board versions.
Best,
Rurik
On 9/28/11 3:16 PM, G Jones wrote:
Hi,
I'm working on getting the ADC83000x2 yellow block working with ROACH 2.
I found that there is some issue with the automatic translation of the
legacy DCM parameters specified by that block to the new MMCM, so I have
made a new version that explicitly invokes an MMCM. I have used the
clock generator wizard to determine the multipliers and divisors, and
since the VCO frequency range spans an octave (600 to 1200 MHz), the
multiplier and divisors will only be valid for an octave range of ADC
clock input frequencies. I have implemented settings that work for ADC
inputs of 800 to 1600 MHz (corresponding to FPGA clocks of 200 to 400
MHz). However, if someone wants to clock their design at a lower rate,
different multipliers and divisors will be needed. Is there an easy way
to set this dynamically based on the requested clock rate?
Glenn
