Hello Renjie, I'm actually not entirely sure about your question, would you mind elaborate it a little bit more for me? You must have read this already( https://casper.berkeley.edu/wiki/Tutorial_10GbE), but just in case you want to check it out again, I guess the information about clocking in the "background" section would be helpful for you.
There are various clocking options available for the roach board, but I believe if your design has ADCs you will need to use one of the adcX_clk ( https://casper.berkeley.edu/wiki/Introduction_to_Simulink). So your roach board will be clocked off the ADC. The interface of your design also runs at this FPGA clock rate. But the CX-4 ports run at fixed 156.25 MHz. These are explained in detail in the 10GbE tutorial. Hope this helps, and P.S. Please correct me if I'm wrong, thanks! -Hong On Fri, Apr 6, 2012 at 12:03 AM, 朱人杰 <[email protected]> wrote: > ** > Dear all, > > When a design included both ADCs and Ten_Gbe, it seems to be more than > one clock region. How to reslove this problem in simulink? > Thank you. > > Best Reguards > Renjie Zhu > > > ------------------------------ > 2012-04-06 > >
