On Tue, May 29, 2012 at 4:45 PM, Laura Vertatschitsch <[email protected]> wrote: > Hey guys, > > I've got several designs where I consistently clock 512 64-bit samples into > the ten gbe0 (v2 block) at a rate of ~14MHz. The fpga clock is running at > 200. It's my understanding that I still should have some room to get faster > data off. I went up by a factor of 2 (the only change in my design) to > clock the data, still only 512 samples, at a new rate of ~28MHz. Not a > single packet is sent, and the tx_afull and tx_overrun flags are > consistently high. I was surprised by this, as I am only creating 4096Bytes > in the frame and I know ~8000B is the limit. I've simulated in Simulink to > be sure that the tx_valid and eof flags are being set when I want. > > Could there be something else going on here? Could the tx_overrun flag also > be set in the event that the buffer cannot clear out the data before the > next data point in?
Yes. If you fill up the internal buffer, you'll get an overrun. tx_afull is a bit problematic -- in my experience, I had to wait a few clocks after filling up the buffer to let some of it drain. (I ended up just ignoring it and counting samples myself.) --Andy
