Hi Ioana Thanks Dave!
I have fixed the typo and push it to github. ( https://github.com/casper-astro/mlib_devel/commit/cb1790fa0e3c750b3f73cf82e80555c1b5f79edc ) Regards Henno On Sat, Jan 12, 2013 at 1:47 AM, Ioana Alexandra Zelko < [email protected]> wrote: > It worked. Thank you! > > > > On Fri, Jan 11, 2013 at 2:57 PM, David MacMahon <[email protected] > > wrote: > >> Hi, Ioana, >> >> On Jan 11, 2013, at 9:34 AM, Ioana Alexandra Zelko wrote: >> >> > ERROR:HDLCompiler:597 - >> "/home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_base/pcores/gbe_udp_v1_00_a/hdl/verilog/gbe_udp.v" >> Line 227: Module gbe_cpu_attach does not have a parameter named C_OPB_DWIDTH >> >> But it does have a parameter named C_OPB_DWISTH! This typo needs to be >> fixed in mlib_devel, but you might want to first fix it in your local build >> copy so that you can finish the current build. Edit the file >> XPS_ROACH2_base/pcores/gbe_udp_v1_00_a/hdl/verilog/gbe_cpu_attach.v. On >> line 12 change "C_OPB_DWISTH" to "C_OPB_DWIDTH" (i.e. change the 'S' to a >> 'D'). Then you can run just the "EDK/ISE/Bitgen step again (i.e. uncheck >> all the other checkboxes in the bee_xps/xasper_xps dialog). >> >> Until this gets fixed in your mlib_devel, this file will need to be >> re-edited every time you re-generate the model (specifically, every time >> the "Copy base package" step runs). >> >> Dave >> >> > -- Henno Kriel DSP Engineer Digital Back End meerKAT SKA South Africa Third Floor The Park Park Road (off Alexandra Road) Pinelands 7405 Western Cape South Africa Latitude: -33.94329 (South); Longitude: 18.48945 (East). (p) +27 (0)21 506 7300 (p) +27 (0)21 506 7365 (direct) (f) +27 (0)21 506 7375 (m) +27 (0)84 504 5050
