Good call. I'll give it a shot and report back :-)
On 01/23/2013 01:22 AM, Henno Kriel wrote:
Hi Ryan
I'm not sure which ADC part is being used, but from the MKID_ADC Test
report it seems the be the TI ADS5474.
From this data sheet the data clock to data delay (t data) is
typically 1.4ns. Your data clock period is 250 / 2 MHz (DDR) = 8 ns.
The IDDR blocks are clocked by the 90deg clock from the vhdl file
adc2x_14_400_interface.vhd.
So the problem is that you are probably violating the setup time on
the IDDR:
Data delay = 1.4 ns
Clock delay = 8ns * 90deg = 2ns.
This gives a setup time of .6 ns (bad). Change the IDDRs to be clocked
with clk (in stead of clk90) in adc2x_14_400_interface.vhd, which
gives you setup time of 2.6ns
and add the constraint to your ucf file:
OFFSET=IN 2.6 ns VALID 4.0 ns BEFORE "*DRDY_I_p" RISING;
OFFSET=IN 2.6 ns VALID 4.0 ns BEFORE "*DRDY_I_p" FALLING;
Hope this helps.
Henno
On Wed, Jan 23, 2013 at 12:11 AM, Ryan Monroe <[email protected]
<mailto:[email protected]>> wrote:
(Looks like casper list does not support attachments. Here are
some links...let's try this again)
http://dl.dropbox.com/u/2832602/adc2x400_issues_histo.jpg
http://dl.dropbox.com/u/2832602/adc2x400_issues.jpg
===============================================
Hey guys,
I'm trying to use the adc2x400-14, a 14-bit ADC part being clocked
at 256 MSPS.
When I run the adc with zero input, everything looks good.
However, if I put in a sine wave (or anything, really) -- I get
this (see figure). Looks like it has a bunch of outliers.
They're not all the same code (see histogram), but they are
coherent with a specific phase of the sine wave (plus or minus n*pi).
This happens in both ADC channels, although this figure is just of
one.
Any ideas? Thanks!
--
Ryan Monroe
904.923.8776 <tel:904.923.8776>
--
Henno Kriel
DSP Engineer
Digital Back End
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