hi Ryan,
another solution for you(if you don't want to change your ucf file):
you can just modify the DCM phase shift parameters of your ADC yellow block
sampling clock by modifying the line 345 (adc2x14_400_interface.vhd )
PHASE_SHIFT => 0, <----- you can set here the appropriate
value: they are explained in the DCM userguide of the virtex5, for example:
if you set the value 32, it will sample your "adc zdock data bus" with a
phase shift of 45 degree. try several value until you get rid of spike in
your plot. for each value you need to generate a new boffile. once you get
it, keep it for the rest of your future design. Of course if you change
your adc sampling clock you will have to make sure that the adc data are
still good.
adc2x14_400_interface.vhd (if you are using the "adc2x14_400" yellow block )
located in your casper xps library :
/home/roach/mlib_git/mlib_devel/xps_base/XPS_ROACH_base/pcores/adc2x14_400_interface_v1_00_a/hdl/vhdl
regards, I hope this trick will help also someone else.
