We are just using the adc5g yellow block from ska-sa/mlib_devel, which i think is the same as that in the sma-wideband/mlib_devel Glenn On Apr 18, 2013 10:27 PM, "Homin Jiang" <[email protected]> wrote:
> Dear Rurik: > > I downloaded the library from github/ska-sa at Jan 21,2013. > Could you specify where is the floating reset line ? that might give me > some hints. > > Dear Mark and Glenn: > > Could you share me what you have done ? That might save me couple of days. > > cheers > homin > > > > On Thu, Apr 18, 2013 at 11:09 PM, Rurik A Primiani < > [email protected]> wrote: > >> Hi Homin, >> >> What version of the yellow block are you using? >> >> We had an issue with the clock not coming through due to a floating reset >> line that was not being driven. This was fixed a while ago on >> sma-wideband/mlib_devel and I believe has also been merged into the main >> casper-astro repository. >> >> Thanks, >> Rurik >> >> >> On 4/18/2013 10:49 AM, John Ford wrote: >> >>> Hi >>>> >>>> Thanks of prompt response >>>> I have compared the schematics of both versions . The clock pins are >>>> kept >>>> the same. >>>> I compiled the bof files using the rev 2 ucf file. >>>> >>> Hi Homin. >>> >>> We are successfully using the ASIAA 5 GS/s ADC and Rev 2 roach together >>> using the ADC clock input. Maybe Glenn Jones or Mark Wagner can comment >>> on the yellow blocks we're using. >>> >>> John >>> >>> Homin >>>> >>>> >>>> Henno Kriel 於 2013年4月18日星期四寫道： >>>> >>>> Hi Homin >>>>> >>>>> There was a change to the routing from the ZDOK pins to the FPGA from >>>>> rev1 >>>>> to rev2. >>>>> Are you still running a design that was compiled for rev1? >>>>> >>>>> Regards >>>>> Henno >>>>> >>>>> >>>>> On Thu, Apr 18, 2013 at 2:22 PM, Homin Jiang >>>>> <[email protected]<**javascript:_e({}, 'cvml', >>>>> '[email protected]');> >>>>> >>>>>> wrote: >>>>>> Hello: >>>>>> >>>>>> After couple of tests, we found that the ADC clock signal is not able >>>>>> enter to the ROACH2 Rev 2. We physically measure the clock pin on ZDOK >>>>>> (F19,F20) of one 5G adc board which was plugged into Rev 1 and then >>>>>> Rev >>>>>> 2. >>>>>> In the Rev 1, there is clock signal, but no signal in the Rev 2. >>>>>> >>>>>> 4 of ROACH2 Rev. 2 have been tested by 10G ethernet bof file which >>>>>> used >>>>>> the system clock. The Rev 2 boards are working well in that case. The >>>>>> only >>>>>> difference i know is the Rev 1 is under tcpborphserver 2 , and the Rev >>>>>> 2 is >>>>>> under tcpborphserver 3. Is there IO bank control in the tcpborphserver >>>>>> 3 ? >>>>>> >>>>>> regards >>>>>> homin jiang >>>>>> >>>>>> >>>>>> >>>>> -- >>>>> Henno Kriel >>>>> >>>>> DSP Engineer >>>>> Digital Back End >>>>> meerKAT >>>>> >>>>> SKA South Africa >>>>> Third Floor >>>>> The Park >>>>> Park Road (off Alexandra Road) >>>>> Pinelands >>>>> 7405 >>>>> Western Cape >>>>> South Africa >>>>> >>>>> Latitude: -33.94329 (South); Longitude: 18.48945 (East). >>>>> >>>>> (p) +27 (0)21 506 7300 >>>>> (p) +27 (0)21 506 7365 (direct) >>>>> (f) +27 (0)21 506 7375 >>>>> (m) +27 (0)84 504 5050 >>>>> >>>>> >>> >>> >> >
