Hi CASPERites,
This work might be of interest to some of you working on packetized correlators. Cheers, Peter From: [email protected] [mailto:[email protected]] On Behalf Of Student Services Sent: Thursday, April 25, 2013 11:22 AM To: [email protected] Subject: [ee-doctorate] Oral Exam Announcement: Glen Gibb Parsing Packet Headers Glen Gibb PhD Oral Defense Department of Electrical Engineering Research Advisor: Prof. Nick McKeown Date: Wednesday May 1st, 2013 Time: 2:00pm (refreshments at 1:45pm) Location: Gates 104 All network devices must parse packet headers to decide how packets should be processed. For example, a 64 x 10Gb/s Ethernet switch must parse 1 billion packets per second to find the headers to use in the forwarding decision. Parsers are simple to specify using a parse graph and can be implemented as a state machine. The parser shares the chip area with many other functions, and so the problem is to design a parser fast enough to process packets at line-rate, while consuming the smallest area and power. Despite the ubiquity of parsers, very little has been written on the design of packet parsers or the tradeoffs between different designs. Is it better to design one fast parser, or several slow parsers? How many bits should the state machine process at a time? What is the cost of making the parser reconfigurable in the field? In my talk I'll describe the tradeoffs in parser design, leading to some design principles for switch and router designers.
