Dear Caspar: I have a design that compiles fine when I have the clock on the MSSGE ROACH block set to sys_clk 100MHz. If I set the clock to dac1_clk, 100MHz, or other clocks I get lots of compile errors of the sort below. Basically, the Xilinx compiler thinks the clock pins are disconnected on many of the blocks. If I set the clock back to sys_clk, it compiles fine again.
Here is an example error. I get many of these. Constructing platform-level connectivity ... ERROR:EDK:4072 - INSTANCE: sys_block_inst, PORT: fab_clk - port is driven by a sourceless connector - /home/oxygen26/TMADDEN/ROACH/projcts/singen/XPS_ROACH_base/system.mhs line 148 I am running in Linux, Matlab R2012b. XSG version is 14.2 Tim Madden Argonne Lab
