Hi all. We have set before ourselves a task to read blocks of data from the FPGA through some shared BRAMs or something, and send it out through the 100 Mbit Ethernet. Does anyone have a good idea for synchronizing the data transfers? I was thinking of using:
1) 2 ping-pong shared FIFOs. Connecting the full bit to a software register and polling to see if it is full, and if so, read it. Yuck. 2) 2 ping pong Shared BRAM buffers, and a software register for each that the FPGA logic sets to note the buffer is full, that is read and then cleared by writing to a different register. Double Yuck. Questions: 1) Is there any performance difference between the 2 options above? 2) What's the best way to read it on the PPC side? 2) Can you select() on the borph register? Any interrupts available? 3) Is there A Better Way not involving 10 gbe? John
