Hi, John, On May 29, 2013, at 8:42 AM, John Ford wrote:
> Does anyone have a good idea for synchronizing the data > transfers? I was thinking of using: > > 1) 2 ping-pong shared FIFOs. Connecting the full bit to a software > register and polling to see if it is full, and if so, read it. Yuck. > > 2) 2 ping pong Shared BRAM buffers, and a software register for each that > the FPGA logic sets to note the buffer is full, that is read and then > cleared by writing to a different register. Double Yuck. > > Questions: > > 1) Is there any performance difference between the 2 options above? I don't think so. Theoretically, I think the reads of a Shared BRAM could be bursted on the EPB, but I don't know whether the EPB/OPB bridge interface supports bursting at all. We basically used a variation of option 2 where the gateware would integrate in one (e.g. the lower) half of a Shared BRAM, then switch to integrate in the other (e.g. the upper) half of the Shared BRAM. An "integration counter" fed a software register. The least significant bit of that counter indicated which half of the BRAM was being integrated into so we would know to read out the other half whenever the bit changed. We also read the integration counter after reading the data to make sure that the bank (i.e. upper or lower half) being integrated into didn't change while we were reading out the data, which could happen with very short integration times. > 2) What's the best way to read it on the PPC side? I think you're stuck with BORPH on ROACH-1. I'd at least make sure that you've set it up to transfer data in binary mode. > 2) Can you select() on the borph register? Any interrupts available? I am 99.9999% sure that you canNOT select() on the /proc file that borph creates for a software register. I am not aware of any way to generate PPC interrupts from the FPGA fabric. > 3) Is there A Better Way not involving 10 gbe? Switch to ROACH2? :-) Dave
