So we took a look at doing this a while ago and xst is run as part of sysgen which makes it hard to single out. Ndgbuild, map, par and trace are run from an xflow script which doesnt help when trying to select a combination of them. I agree that this would be a useful feature. Ill take better look at it.
Haoxuan you could try commenting out most of xps_base/XPS_ROACH_base/etc/fast_runtime.opt and then also stop bitgen from running. Wesley New South African SKA Project +2721 506 7365 www.ska.ac.za On Tue, Jul 2, 2013 at 5:25 AM, Ryan Monroe <ryan.m.mon...@gmail.com> wrote: > Wait until it hits MAP and hit CTRL-C? Then do your business and it'll > usually skip synthesis on the next run.... > > --Ryan Monroe626.773.0805 > > On 07/01/2013 05:18 PM, Jeff Zheng wrote: > > Hi Ryan, > Thanks a lot for the quick answer! Given the current capser_xps, is there > any command I can skip to avoid placement? Does IP Synthesis finish the > synthesized design? > > Jeff > > > On Mon, Jul 1, 2013 at 12:37 PM, Ryan Monroe <ryan.m.mon...@gmail.com>wrote: > >> Nope! But we should change the choices on Casper xps (imo) to >> >> Update design >> XSG >> (Everything "copy base package" through Synthesis) >> The rest >> On Jul 1, 2013 9:28 AM, "Haoxuan Zheng" <jef...@mit.edu> wrote: >> >>> Hi Casper, >>> [Question]: >>> Is there a way to ask casper_xps to finish synthesized design and stop >>> there (meaning not to attempt placement), and I take over in PlanAhead? >>> This will save me a few hours each run. I checked the casper wiki for >>> casper_xps but I'm not sure which step corresponds to completion of >>> synthesized design. >>> >>> [Background]: >>> We have an X-engine design that is guaranteed not to meet timing in >>> casper_xps compiling, but we have found a reliable floor planning strategy >>> (pblocks etc) in PlanAhead to make it compile. I have been debugging it >>> thus making minor changes that makes no difference as far as compiling is >>> concerned, so it is a waste of time in casper_xps to go from a synthesised >>> design to an implemented design, given that its implementation will fail >>> timing anyways. (I'm using planahead language here, sorry if that's not >>> clear.) >>> >>> Thank you guys so much! >>> Jeff >>> >> > >
