I am getting the following error when compiling a simple ADC design on a ROACH2 with one ADC16x250:
ERROR:LIT:667 - Block 'MMCM_ADV symbol "physical_group_adc_test_adc16x250_8/adc_test_adc16x250_8/bufg_i<3>/adc_test_ adc16x250_8/adc_test_adc16x250_8/adc_mmcm_0/mmcm_adv_inst" (output signal=adc_test_adc16x250_8/adc_test_adc16x250_8/bufg_i<3>)' has its target frequency, FVCO, out of range. Valid FVCO range for speed grade "-1" is 600MHz - 1200MHz. The computed FCVO is a function of the input frequency CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The CLKIN_PERIOD attribute may have been set by ngdbuild based on the user specified PERIOD constraint. The current calculated FVCO is 500.000000 MHz. Reference the V6 architecture Users Guide or search the Xilinx Answer Records database for the error code. Questions: 1) How do I clear this error? 2) How do I explicitly set the ADC sample rate and FPGA main clock frequency? 3) How are clocks inferred and what are the limitations on inferred clocks? Thanks, -Joe Kujawski -- ************************************** * Joe Kujawski * Siena College * Dept. of Physics and Astronomy, RB 113 * 515 Loudon Road * Loudonville, NY 12211-1462 * * Email: [email protected] * Phone: 518-782-6885 * Fax: 518-783-2986 **************************************
