Hi, Joe, On Sep 23, 2013, at 8:13 AM, Kujawski, Joseph wrote:
> I am getting the following error when compiling a simple ADC design on a > ROACH2 with one ADC16x250: > > ERROR:LIT:667 - Block 'MMCM_ADV symbol > > "physical_group_adc_test_adc16x250_8/adc_test_adc16x250_8/bufg_i<3>/adc_test_ > > adc16x250_8/adc_test_adc16x250_8/adc_mmcm_0/mmcm_adv_inst" (output > signal=adc_test_adc16x250_8/adc_test_adc16x250_8/bufg_i<3>)' has its > target > frequency, FVCO, out of range. Valid FVCO range for speed grade "-1" is > 600MHz - 1200MHz. The computed FCVO is a function of the input frequency > CLKIN1_PERIOD, the division factor DIVCLK_DIVIDE, and the CLKFBOUT_MULT_F > attribute (FVCO = 1000*CLKFBOUT_MULT_F/(CLKIN1_PERIOD*DIVCLK_DIVIDE)). The > > CLKIN_PERIOD attribute may have been set by ngdbuild based on the user > specified PERIOD constraint. The current calculated FVCO is 500.000000 > MHz. > Reference the V6 architecture Users Guide or search the Xilinx Answer > Records > database for the error code. > > Questions: > 1) How do I clear this error? The "User IP Clock Rate" that you specified in XSG block's dialog is out of range for the ADC16 board. For the ADC16, the "User IP Clock Range" must be in the range 135 MHz to 240 MHz. This range corresponds to an ADC sample clock range of 135-240 MHz in 16 input mode, or 270-480 in 8 input mode, or 540-960 MHz in 4 input mode. The wiki mentions a 67.5 to 120 MSPS range (in 16 input mode), but support for that range (and corresponding ranges in 8 or 4 input modes) has not yet been added. I would be nice if this block had better sanity checking up front so you didn't have to go through the whole compile just to find out the clock frequency is invalid. Patches welcome. > 2) How do I explicitly set the ADC sample rate and FPGA main clock frequency? For the ADC16, you only specify the "User IP Clock Rate" in the XSG block (and pick "adc0_clk" as the "User IP Clock Source". This rate corresponds to the sample rate for the ADC16 board in 16 input mode. The actual ADC clock rate that you need to apply depends on how you initialize the ADC16 after programming the FPGA. For the default 16-input mode, the User IP Clock Rate (aka the fabric clock rate) is the same as the ADC sample clock frequency. > 3) How are clocks inferred and what are the limitations on inferred clocks? The fabric clocking is inferred from the frequency specified in the XSG block. It is your responsibility to ensure that the ADC sample clock you provide and the ADC16 initialization you perform result in a compatible frequency for the FPGA. For the default 16-input mode, this means that the ADC16 sample clock must be the same frequency as the fabric clock. Hope this helps, Dave
