The timing was so bad that it didn't get beyond the mapping stage.
Follow the instructions in the error message:
"Please use the Timing Analyzer (GUI) or TRCE (command line) with the
Mapped NCD"

so run the $XILINX/settings64.sh and then timingan and use the "open
design" option to open the system_map.ncd (or something like that, I'm
going from memory) in the implementation directory.

Glenn

On Wed, Oct 2, 2013 at 7:39 AM, Andrea Mattana <matt...@ira.inaf.it> wrote:
> Hi all,
>
> I'm compiling a model file for ROACH1 but I have to solve some timing
> constraints which are not met. Unfortunately, the system.twx file to
> be opened with the timing analyzer which should be found in
> XPS_R..BASE/implementations/ is missing.
>
> Do you have an idea?
>
> Cheers,
> Andrea
>
>
>
> Running delay-based LUT packing...
> Updating timing models...
> ERROR:Pack:1653 - At least one timing constraint is impossible to meet because
>    component delays alone exceed the constraint. A timing constraint summary
>    below shows the failing constraints (preceded with an Asterisk (*)). Please
>    use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD 
> and
>    PCF files to identify which constraints and paths are failing because of 
> the
>    component delays alone. If the failing path(s) is mapped to Xilinx 
> components
>    as expected, consider relaxing the constraint. If it is not mapped to
>    components as expected, re-evaluate your HDL and how synthesis is 
> optimizing
>    the path. To allow the tools to bypass this error, set the environment
>    variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.
>
>
>    For more information about the Timing Analyzer, consult the Xilinx Timing
>    Analyzer Reference manual; for more information on TRCE, consult the Xilinx
>    Command Line Tools User Guide "TRACE" chapter.
> INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more
>    information, see the TSI report.  Please consult the Xilinx Command Line
>    Tools User Guide for information on generating a TSI report.
> INFO:Timing:3284 - This timing report was generated using estimated delay
>    information.  For accurate numbers, please refer to the post Place and 
> Route
>    timing report.
> Number of Timing Constraints that were not applied: 3
>
> Asterisk (*) preceding a constraint indicates it was not met.
>    This may be due to a setup or hold violation.
>
> ----------------------------------------------------------------------------------------------------------
>   Constraint                                |    Check    | Worst Case
> |  Best Case | Timing |   Timing
>                                             |             |    Slack
> | Achievable | Errors |    Score
> ----------------------------------------------------------------------------------------------------------
> * PERIOD analysis for net "mad_corr_beam_x6 | SETUP       |
> -3.440ns|     9.690ns|     113|      272325
>   4_adc_fab_phase_gen/mad_corr_beam_x64_adc | HOLD        |
> -0.179ns|            |    6891|      366231
>   _fab_phase_gen/CLK0_BUF" derived from  PE |             |
> |            |        |
>   RIOD analysis for net "mad_corr_beam_x64_ |             |
> |            |        |
>   adc/fab_clk1" derived from NET "mad_corr_ |             |
> |            |        |
>   beam_x64_adc/mad_corr_beam_x64_adc/x64_ad |             |
> |            |        |
>   c_infrastructure_inst/adc_clk_ibufds" PER |             |
> |            |        |
>   IOD = 4.1667 ns HIGH 50% multiplied by 1. |             |
> |            |        |
>   50 to 6.250 nS and duty cycle corrected t |             |
> |            |        |
>   o HIGH 3.125 nS   duty cycle corrected to |             |
> |            |        |
>    6.250 nS  HIGH 3.125 nS                  |             |
> |            |        |
> ----------------------------------------------------------------------------------------------------------
> * TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" | SETUP       |
> 3.803ns|     2.597ns|       0|           0
>    156.25 MHz HIGH 50%                      | HOLD        |
> -1.513ns|            |     218|      146110
> ----------------------------------------------------------------------------------------------------------
> * TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt | SETUP       |
> 5.500ns|     0.900ns|       0|           0
>   _clk_mult_2_b" 156.25 MHz HIGH 50%        | HOLD        |
> -0.204ns|            |      18|        3672
> ----------------------------------------------------------------------------------------------------------
>   NET "mad_corr_beam_x64_adc/mad_corr_beam_ | MINLOWPULSE |
> 0.566ns|     3.600ns|       0|           0
>   x64_adc/x64_adc_infrastructure_inst/adc_c |             |
> |            |        |
>   lk_ibufds" PERIOD = 4.1667 ns HIGH 50%    |             |
> |            |        |
> ----------------------------------------------------------------------------------------------------------
>   PERIOD analysis for net "mad_corr_beam_x6 | SETUP       |
> 5.132ns|     1.118ns|       0|           0
>   4_adc/fab_clk1" derived from  NET "mad_co | HOLD        |
> 0.195ns|            |       0|           0
>   rr_beam_x64_adc/mad_corr_beam_x64_adc/x64 | MINLOWPULSE |
> 2.249ns|     4.000ns|       0|           0
>   _adc_infrastructure_inst/adc_clk_ibufds"  |             |
> |            |        |
>   PERIOD = 4.1667 ns HIGH 50%  multiplied b |             |
> |            |        |
>   y 1.50 to 6.250 nS and duty cycle correct |             |
> |            |        |
>   ed to HIGH 3.125 nS                       |             |
> |            |        |
> ----------------------------------------------------------------------------------------------------------
>   TS_sys_clk_n = PERIOD TIMEGRP "sys_clk_n" | MINPERIOD   |
> 1.668ns|     8.332ns|       0|           0
>    100 MHz HIGH 50%                         |             |
> |            |        |
> ----------------------------------------------------------------------------------------------------------
>   PERIOD analysis for net "mad_corr_beam_x6 | SETUP       |
> 2.874ns|     1.292ns|       0|           0
>   4_adc/mad_corr_beam_x64_adc/x64_adc_infra | HOLD        |
> 0.148ns|            |       0|           0
>   structure_inst/adc_clk_dcm" derived from  | MINPERIOD   |
> 1.945ns|     2.221ns|       0|           0
>    NET "mad_corr_beam_x64_adc/mad_corr_beam |             |
> |            |        |
>   _x64_adc/x64_adc_infrastructure_inst/adc_ |             |
> |            |        |
>   clk_ibufds" PERIOD = 4.1667 ns HIGH 50%   |             |
> |            |        |
>   duty cycle corrected to 4.167 nS  HIGH 2. |             |
> |            |        |
>   083 nS                                    |             |
> |            |        |
> ----------------------------------------------------------------------------------------------------------
>   NET "epb_cs_n_IBUF" MAXDELAY = 4 ns       | MAXDELAY    |
> 4.000ns|     0.000ns|       0|           0
> ----------------------------------------------------------------------------------------------------------
>   TS_RAM_FF = MAXDELAY FROM TIMEGRP "RAMSOU | SETUP       |
> 4.580ns|     1.670ns|       0|           0
>   RCE" TO TIMEGRP "FFDEST" 6.25 ns DATAPATH | HOLD        |
> 1.175ns|            |       0|           0
>   ONLY                                      |             |
> |            |        |
> ----------------------------------------------------------------------------------------------------------
>   NET "mad_corr_beam_x64_adc/mad_corr_beam_ | N/A         |
> N/A|         N/A|     N/A|         N/A
>   x64_adc/x64_adc_infrastructure_inst/adc_c |             |
> |            |        |
>   lk_ibufds" PERIOD = 4.1667 ns HIGH 50%    |             |
> |            |        |
> ----------------------------------------------------------------------------------------------------------
>
>
> Derived Constraint Report
> Derived Constraints for
> mad_corr_beam_x64_adc/mad_corr_beam_x64_adc/x64_adc_infrastructure_inst/adc_clk_ibufds
> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
> ----------+
> |                               |   Period    |       Actual Period
>    |      Timing Errors        |      Paths
> Analyzed       |
> |           Constraint          | Requirement
> |-------------+-------------|-------------+-------------|-------------+-------------|
> |                               |             |   Direct    |
> Derivative  |   Direct    | Derivative  |   Direct    |
> Derivative  |
> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
> ----------+
> |mad_corr_beam_x64_adc/mad_corr_|      4.167ns|      3.600ns|
> 6.460ns|            0|         7004|            0|
>   1035514|
> |beam_x64_adc/x64_adc_infrastruc|             |             |
>    |             |             |             |
>          |
> |ture_inst/adc_clk_ibufds       |             |             |
>    |             |             |             |
>          |
> | mad_corr_beam_x64_adc/mad_corr|      4.167ns|      2.221ns|
> N/A|            0|            0|         4528|
>         0|
> | _beam_x64_adc/x64_adc_infrastr|             |             |
>    |             |             |             |
>          |
> | ucture_inst/adc_clk_dcm       |             |             |
>    |             |             |             |
>          |
> | mad_corr_beam_x64_adc/fab_clk1|      6.250ns|      4.000ns|
> 9.690ns|            0|         7004|         1375|
>   1029611|
> |  mad_corr_beam_x64_adc_fab_pha|      6.250ns|      9.690ns|
> N/A|         7004|            0|      1029611|
>         0|
> |  se_gen/mad_corr_beam_x64_adc_|             |             |
>    |             |             |             |
>          |
> |  fab_phase_gen/CLK0_BUF       |             |             |
>    |             |             |             |
>          |
> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+---
> ----------+
>
> 3 constraints not met.
> INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
>    constraint does not cover any paths or that it has no requested value.
>
>
>
> Mapping completed.
> See MAP report file "system_map.mrp" for details.
> Problem encountered during the packing phase.
>
> Design Summary
> --------------
> Number of errors   :   1
> Number of warnings :2201
> ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
> gmake: *** [__xps/system_routed] Error 1
>
> --
> Andrea Mattana
>
> I.N.A.F. - Istituto di Radioastronomia
> Radiotelescopi di Medicina
> Via Fiorentina, 3513 - 40059 Medicina (Bo)
> Tel. 051/6965834      Fax. 051/6965810
>

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