mmm yes I think that's the problem, I have read the system generator reference manual at the delay block page and should be definitely a problem to have big delay coupled with big data bus width.
Thanks, I will try i a different way and will report the improvements (hopefully). Andrea 2013/10/2 Andrea Mattana <[email protected]>: > Thanks Jack, > > can be a z^-2048 delay?? > > > Andrea > > 2013/10/2 Jack Hickish <[email protected]>: >> Hey Andrea, >> >> I think (http://www.xilinx.com/support/answers/23165.html) the ngc >> file is all you're going to get, unless you run the compile again with >> the XIL_TIMING_ALLOW_IMPOSSIBLE variable set to 1. >> >> Your error is some specific component that has impossible timing >> constraints -- it's not just general routing difficulties. I don't >> think it can be ADC related unless you've changed the ADC parameters >> since your last compile. I think it has to be some block you've >> changed the parameters of or added since your last successful compile >> -- embedded multipliers with low latency and really large input >> bitwidths are one example of a common block which I've seen throw this >> error. I'm sure there are plenty of others... >> >> Cheers, >> Jack >> >> On 2 October 2013 15:34, Andrea Mattana <[email protected]> wrote: >>> I'm sure, the directory is correct, because I do that very often, but >>> in this case the system.twx is really missing. The only file readable >>> from the timingan is a ngc file but I don't know how to investigate >>> timing with that. >>> >>> Can be an issue related to the ADC or some resources ended? This is >>> the last succesfully compilation, I have added few blocks after that: >>> >>> Design Summary: >>> Number of errors: 0 >>> Number of warnings: 2216 >>> Slice Logic Utilization: >>> Number of Slice Registers: 34,241 out of 58,880 58% >>> Number used as Flip Flops: 34,239 >>> Number used as Latch-thrus: 2 >>> Number of Slice LUTs: 28,529 out of 58,880 48% >>> Number used as logic: 23,304 out of 58,880 39% >>> Number using O6 output only: 17,536 >>> Number using O5 output only: 4,428 >>> Number using O5 and O6: 1,340 >>> Number used as Memory: 4,890 out of 24,320 20% >>> Number used as Dual Port RAM: 304 >>> Number using O6 output only: 188 >>> Number using O5 and O6: 116 >>> Number used as Shift Register: 4,586 >>> Number using O6 output only: 4,586 >>> Number used as exclusive route-thru: 335 >>> Number of route-thrus: 4,992 >>> Number using O6 output only: 4,747 >>> Number using O5 output only: 241 >>> Number using O5 and O6: 4 >>> >>> Slice Logic Distribution: >>> Number of occupied Slices: 12,032 out of 14,720 81% >>> Number of LUT Flip Flop pairs used: 40,207 >>> Number with an unused Flip Flop: 5,966 out of 40,207 14% >>> Number with an unused LUT: 11,678 out of 40,207 29% >>> Number of fully used LUT-FF pairs: 22,563 out of 40,207 56% >>> Number of unique control sets: 584 >>> Number of slice register sites lost >>> to control set restrictions: 1,187 out of 58,880 2% >>> >>> A LUT Flip Flop pair for this architecture represents one LUT paired with >>> one Flip Flop within a slice. A control set is a unique combination of >>> clock, reset, set, and enable signals for a registered element. >>> The Slice Logic Distribution report is not meaningful if the design is >>> over-mapped for a non-slice resource or if Placement fails. >>> OVERMAPPING of BRAM resources should be ignored if the design is >>> over-mapped for a non-BRAM resource or if placement fails. >>> >>> IO Utilization: >>> Number of bonded IOBs: 151 out of 640 23% >>> Number of LOCed IOBs: 151 out of 151 100% >>> IOB Flip Flops: 114 >>> Number of bonded IPADs: 36 out of 50 72% >>> Number of bonded OPADs: 32 out of 32 100% >>> >>> Specific Feature Utilization: >>> Number of BlockRAM/FIFO: 219 out of 244 89% >>> Number using BlockRAM only: 219 >>> Total primitives used: >>> Number of 36k BlockRAM used: 175 >>> Number of 18k BlockRAM used: 77 >>> Total Memory used (KB): 7,686 out of 8,784 87% >>> Number of BUFG/BUFGCTRLs: 12 out of 32 37% >>> Number used as BUFGs: 12 >>> Number of IDELAYCTRLs: 6 out of 22 27% >>> Number of BUFDSs: 2 out of 8 25% >>> Number of CRC64s: 2 out of 16 12% >>> Number of DCM_ADVs: 4 out of 12 33% >>> Number of DSP48Es: 233 out of 640 36% >>> Number of GTP_DUALs: 8 out of 8 100% >>> Number of PLL_ADVs: 2 out of 6 33% >>> >>> Average Fanout of Non-Clock Nets: 2.16 >>> >>> Peak Memory Usage: 1931 MB >>> Total REAL time to MAP completion: 13 mins 41 secs >>> Total CPU time to MAP completion: 13 mins 33 secs >>> >>> Mapping completed. >>> See MAP report file "system_map.mrp" for details. >>> >>> >>> >>> #----------------------------------------------# >>> # Starting program par >>> # par -ise ../__xps/ise/system.ise -xe n -w -ol high system_map.ncd >>> system.ncd >>> system.pcf >>> #----------------------------------------------# >>> Release 11.4 - par L.68 (lin64) >>> Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. >>> PMSPEC -- Overriding Xilinx file >>> </opt/Xilinx/11.1/EDK/data/parBmgr.acd> with local file >>> </opt/Xilinx/11.1/ISE/data/parBmgr.acd> >>> >>> >>> Loading device for application Rf_Device from file '5vsx95t.nph' in >>> environment >>> /opt/Xilinx/11.1/ISE:/opt/Xilinx/11.1/EDK. >>> "system" is an NCD, version 3.2, device xc5vsx95t, package ff1136, speed >>> -1 >>> >>> Constraints file: system.pcf. >>> "system" is an NCD, version 3.2, device xc5vsx95t, package ff1136, speed >>> -1 >>> WARNING:ConstraintSystem:65 - Constraint <NET >>> >>> "mad_corr_beam_x64_adc/mad_corr_beam_x64_adc/x64_adc_infrastructure_inst/adc_clk_ibufds" >>> PERIOD = 4.1667 ns >>> HIGH 50%;> [system.pcf(10135)] overrides constraint <NET >>> >>> "mad_corr_beam_x64_adc/mad_corr_beam_x64_adc/x64_adc_infrastructure_inst/adc_clk_ibufds" >>> PERIOD = 4.1667 ns >>> HIGH 50%;> [system.pcf(10132)]. >>> >>> >>> Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to >>> 85.000 Celsius) >>> Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) >>> >>> INFO:Timing:3386 - Intersecting Constraints found and resolved. For >>> more information, see the TSI report. Please >>> consult the Xilinx Command Line Tools User Guide for information on >>> generating a TSI report. >>> >>> Device speed data version: "PRODUCTION 1.66 2009-11-16". >>> >>> >>> >>> Device Utilization Summary: >>> >>> Number of BUFDSs 2 out of 8 25% >>> Number of BUFGs 12 out of 32 37% >>> Number of CRC64s 2 out of 16 12% >>> Number of DCM_ADVs 4 out of 12 33% >>> Number of DSP48Es 233 out of 640 36% >>> Number of GTP_DUALs 8 out of 8 100% >>> Number of IDELAYCTRLs 6 out of 22 27% >>> Number of ILOGICs 92 out of 800 11% >>> Number of External IOBs 151 out of 640 23% >>> Number of LOCed IOBs 151 out of 151 100% >>> >>> Number of IODELAYs 44 out of 800 5% >>> Number of External IPADs 36 out of 690 5% >>> Number of LOCed IPADs 36 out of 36 100% >>> >>> Number of OLOGICs 22 out of 800 2% >>> Number of External OPADs 32 out of 32 100% >>> Number of LOCed OPADs 32 out of 32 100% >>> >>> Number of PLL_ADVs 2 out of 6 33% >>> Number of RAMB18X2s 44 out of 244 18% >>> Number of RAMB36SDP_EXPs 10 out of 244 4% >>> Number of RAMB36_EXPs 165 out of 244 67% >>> Number of Slice Registers 34241 out of 58880 58% >>> Number used as Flip Flops 34239 >>> Number used as Latches 0 >>> Number used as LatchThrus 2 >>> >>> Number of Slice LUTS 28529 out of 58880 48% >>> Number of Slice LUT-Flip Flop pairs 40207 out of 58880 68% >>> >>> >>> Overall effort level (-ol): High >>> Router effort level (-rl): High >>> >>> Starting initial Timing Analysis. REAL time: 35 secs >>> Finished initial Timing Analysis. REAL time: 36 secs >>> >>> Starting Router >>> >>> >>> Wirelength Stats for nets on all pins. NumPins: 138867 >>> >>> Phase 1 : 205081 unrouted; REAL time: 41 secs >>> >>> Phase 2 : 125991 unrouted; REAL time: 55 secs >>> >>> Phase 3 : 38237 unrouted; REAL time: 1 mins 51 secs >>> >>> Phase 4 : 38256 unrouted; (Setup:0, Hold:38041, Component Switching >>> Limit:0) REAL time: 2 mins >>> >>> Updating file: system.ncd with current fully routed design. >>> >>> Phase 5 : 0 unrouted; (Setup:0, Hold:35039, Component Switching >>> Limit:0) REAL time: 3 mins 10 secs >>> >>> Phase 6 : 0 unrouted; (Setup:0, Hold:35039, Component Switching >>> Limit:0) REAL time: 3 mins 10 secs >>> >>> Phase 7 : 0 unrouted; (Setup:0, Hold:35039, Component Switching >>> Limit:0) REAL time: 3 mins 10 secs >>> >>> Phase 8 : 0 unrouted; (Setup:0, Hold:35039, Component Switching >>> Limit:0) REAL time: 3 mins 10 secs >>> >>> Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) >>> REAL time: 3 mins 23 secs >>> >>> Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) >>> REAL time: 3 mins 38 secs >>> Total REAL time to Router completion: 3 mins 38 secs >>> Total CPU time to Router completion: 3 mins 38 secs >>> >>> Partition Implementation Status >>> ------------------------------- >>> >>> No Partitions were found in this design. >>> >>> ------------------------------- >>> >>> Generating "PAR" statistics. >>> >>> ************************** >>> Generating Clock Report >>> ************************** >>> >>> +---------------------+--------------+------+------+------------+-------------+ >>> | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max >>> Delay(ns)| >>> +---------------------+--------------+------+------+------------+-------------+ >>> | adc0_clk | BUFGCTRL_X0Y4| No | 9822 | 0.904 | 2.444 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> | epb_clk | BUFGCTRL_X0Y1| No | 840 | 0.822 | 2.354 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> | mgt_clk_0 |BUFGCTRL_X0Y25| No | 773 | 0.695 | 2.320 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> | adc_clk_4x_6d |BUFGCTRL_X0Y30| No | 166 | 0.661 | 2.185 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> |mad_corr_beam_x64_ad | | | | | >>> | >>> | c/adc_clk0 |BUFGCTRL_X0Y29| No | 616 | 0.824 | 2.349 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> |xaui_infrastructure_ | | | | | >>> | >>> | inst/mgt_clk_1 | BUFGCTRL_X0Y3| No | 16 | 0.243 | 2.157 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> |xaui_infrastructure_ | | | | | >>> | >>> |inst/xaui_infrastruc | | | | | >>> | >>> |ture_inst/mgt_clk_mu | | | | | >>> | >>> | lt_2_t | BUFGCTRL_X0Y2| No | 16 | 0.243 | 2.157 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> |infrastructure_inst/ | | | | | >>> | >>> | dly_clk |BUFGCTRL_X0Y27| No | 6 | 0.173 | 2.140 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> |xaui_infrastructure_ | | | | | >>> | >>> |inst/xaui_infrastruc | | | | | >>> | >>> |ture_inst/mgt_clk_mu | | | | | >>> | >>> | lt_2_b |BUFGCTRL_X0Y26| No | 16 | 0.243 | 2.157 >>> | >>> +---------------------+--------------+------+------+------------+-------------+ >>> >>> * Net Skew is the difference between the minimum and maximum routing >>> only delays for the net. Note this is different from Clock Skew which >>> is reported in TRCE timing report. Clock Skew is the difference between >>> the minimum and maximum path delays which includes logic delays. >>> >>> Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) >>> >>> Number of Timing Constraints that were not applied: 3 >>> >>> Asterisk (*) preceding a constraint indicates it was not met. >>> This may be due to a setup or hold violation. >>> >>> ---------------------------------------------------------------------------------------------------------- >>> Constraint | Check | Worst Case >>> | Best Case | Timing | Timing >>> | | Slack >>> | Achievable | Errors | Score >>> ---------------------------------------------------------------------------------------------------------- >>> PERIOD analysis for net "mad_corr_beam_x6 | SETUP | >>> 0.025ns| 6.225ns| 0| 0 >>> 4_adc_fab_phase_gen/mad_corr_beam_x64_adc | HOLD | >>> 0.109ns| | 0| 0 >>> _fab_phase_gen/CLK0_BUF" derived from PE | | >>> | | | >>> RIOD analysis for net "mad_corr_beam_x64_ | | >>> | | | >>> adc/fab_clk1" derived from NET "ma | | >>> | | | >>> d_corr_beam_x64_adc/mad_corr_beam_x64_adc | | >>> | | | >>> /x64_adc_infrastructure_inst/adc_clk_ibuf | | >>> | | | >>> ds" PERIOD = 4.1667 ns HIGH 50% | | >>> | | | >>> ---------------------------------------------------------------------------------------------------------- >>> PERIOD analysis for net "mad_corr_beam_x6 | SETUP | >>> 0.053ns| 4.113ns| 0| 0 >>> 4_adc/mad_corr_beam_x64_adc/x64_adc_infra | HOLD | >>> 0.306ns| | 0| 0 >>> structure_inst/adc_clk_dcm" derived from | | >>> | | | >>> NET "mad_corr_beam_x64_adc/mad_co | | >>> | | | >>> rr_beam_x64_adc/x64_adc_infrastructure_in | | >>> | | | >>> st/adc_clk_ibufds" PERIOD = 4.1667 | | >>> | | | >>> ns HIGH 50% | | >>> | | | >>> ---------------------------------------------------------------------------------------------------------- >>> TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" | SETUP | >>> 0.101ns| 6.299ns| 0| 0 >>> 156.25 MHz HIGH 50% | HOLD | >>> 0.130ns| | 0| 0 >>> ---------------------------------------------------------------------------------------------------------- >>> PERIOD analysis for net "mad_corr_beam_x6 | SETUP | >>> 0.140ns| 6.110ns| 0| 0 >>> 4_adc/fab_clk1" derived from NET | HOLD | >>> 0.335ns| | 0| 0 >>> "mad_corr_beam_x64_adc/mad_corr_beam_x64_ | | >>> | | | >>> adc/x64_adc_infrastructure_inst/adc_clk_i | | >>> | | | >>> bufds" PERIOD = 4.1667 ns HIGH 50% | | >>> | | | >>> ---------------------------------------------------------------------------------------------------------- >>> NET "mad_corr_beam_x64_adc/mad_co | MINLOWPULSE | >>> 0.566ns| 3.600ns| 0| 0 >>> rr_beam_x64_adc/x64_adc_infrastructure_in | | >>> | | | >>> st/adc_clk_ibufds" PERIOD = 4.166 | | >>> | | | >>> 7 ns HIGH 50% | | >>> | | | >>> ---------------------------------------------------------------------------------------------------------- >>> TS_sys_clk_n = PERIOD TIMEGRP "sys_clk_n" | MINPERIOD | >>> 1.668ns| 8.332ns| 0| 0 >>> 100 MHz HIGH 50% | | >>> | | | >>> ---------------------------------------------------------------------------------------------------------- >>> NET "epb_cs_n_IBUF" MAXDELAY = 4 ns | MAXDELAY | >>> 1.701ns| 2.299ns| 0| 0 >>> ---------------------------------------------------------------------------------------------------------- >>> TS_RAM_FF = MAXDELAY FROM TIMEGRP "RAMSOU | SETUP | >>> 1.769ns| 4.481ns| 0| 0 >>> RCE" TO TIMEGRP "FFDEST" 6.25 ns | HOLD | >>> 1.465ns| | 0| 0 >>> DATAPATHONLY | | >>> | | | >>> ---------------------------------------------------------------------------------------------------------- >>> TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt | SETUP | >>> 2.059ns| 4.341ns| 0| 0 >>> _clk_mult_2_b" 156.25 MHz HIGH 50% | HOLD | >>> 1.456ns| | 0| 0 >>> ---------------------------------------------------------------------------------------------------------- >>> NET "mad_corr_beam_x64_adc/mad_co | N/A | >>> N/A| N/A| N/A| N/A >>> rr_beam_x64_adc/x64_adc_infrastructure_in | | >>> | | | >>> st/adc_clk_ibufds" PERIOD = 4.166 | | >>> | | | >>> 7 ns HIGH 50% | | >>> | | | >>> ---------------------------------------------------------------------------------------------------------- >>> >>> >>> Derived Constraint Report >>> Derived Constraints for >>> mad_corr_beam_x64_adc/mad_corr_beam_x64_adc/x64_adc_infrastructure_inst/adc_clk_ibufds >>> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ >>> | | Period | Actual Period >>> | Timing Errors | Paths Analyzed | >>> | Constraint | Requirement >>> |-------------+-------------|-------------+-------------|-------------+-------------| >>> | | | Direct | >>> Derivative | Direct | Derivative | Direct | Derivative | >>> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ >>> |mad_corr_beam_x64_adc/mad_corr_| 4.167ns| 3.600ns| >>> 4.150ns| 0| 0| 0| 767464| >>> |beam_x64_adc/x64_adc_infrastruc| | | >>> | | | | | >>> |ture_inst/adc_clk_ibufds | | | >>> | | | | | >>> | mad_corr_beam_x64_adc/mad_corr| 4.167ns| 4.113ns| >>> N/A| 0| 0| 4528| 0| >>> | _beam_x64_adc/x64_adc_infrastr| | | >>> | | | | | >>> | ucture_inst/adc_clk_dcm | | | >>> | | | | | >>> | mad_corr_beam_x64_adc/fab_clk1| 6.250ns| 6.110ns| >>> 6.225ns| 0| 0| 1375| 761561| >>> | mad_corr_beam_x64_adc_fab_pha| 6.250ns| 6.225ns| >>> N/A| 0| 0| 761561| 0| >>> | se_gen/mad_corr_beam_x64_adc_| | | >>> | | | | | >>> | fab_phase_gen/CLK0_BUF | | | >>> | | | | | >>> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ >>> >>> All constraints were met. >>> INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the >>> constraint does not cover any paths or that it has no requested value. >>> >>> >>> Generating Pad Report. >>> >>> All signals are completely routed. >>> >>> Total REAL time to PAR completion: 3 mins 49 secs >>> Total CPU time to PAR completion: 3 mins 48 secs >>> >>> Peak Memory Usage: 1487 MB >>> >>> Placer: Placement generated during map. >>> Routing: Completed - No errors found. >>> Timing: Completed - No errors found. >>> >>> Number of error messages: 0 >>> Number of warning messages: 1 >>> Number of info messages: 1 >>> >>> Writing design to file system.ncd >>> >>> Andrea >>> >>> 2013/10/2 John Ford <[email protected]>: >>>>> Hi all, >>>>> >>>>> I'm compiling a model file for ROACH1 but I have to solve some timing >>>>> constraints which are not met. Unfortunately, the system.twx file to >>>>> be opened with the timing analyzer which should be found in >>>>> XPS_R..BASE/implementations/ is missing. >>>> >>>> Hmm. If it got as far as the snapshot below, the .twx file should have >>>> been created. >>>> >>>> Are you looking in the directory created by the compile and not the one in >>>> the library? That is: >>>> >>>> .../<modelname>/XPS_ROACH_base/implementation/system.twx >>>> >>>> and not >>>> >>>> .../mlib_devel/xps_base/XPS_ROACH_base/implementation >>>> >>>> John >>>> >>>>> >>>>> Do you have an idea? >>>>> >>>>> Cheers, >>>>> Andrea >>>>> >>>>> >>>>> >>>>> Running delay-based LUT packing... >>>>> Updating timing models... >>>>> ERROR:Pack:1653 - At least one timing constraint is impossible to meet >>>>> because >>>>> component delays alone exceed the constraint. A timing constraint >>>>> summary >>>>> below shows the failing constraints (preceded with an Asterisk (*)). >>>>> Please >>>>> use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped >>>>> NCD and >>>>> PCF files to identify which constraints and paths are failing because >>>>> of the >>>>> component delays alone. If the failing path(s) is mapped to Xilinx >>>>> components >>>>> as expected, consider relaxing the constraint. If it is not mapped to >>>>> components as expected, re-evaluate your HDL and how synthesis is >>>>> optimizing >>>>> the path. To allow the tools to bypass this error, set the environment >>>>> variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1. >>>>> >>>>> >>>>> For more information about the Timing Analyzer, consult the Xilinx >>>>> Timing >>>>> Analyzer Reference manual; for more information on TRCE, consult the >>>>> Xilinx >>>>> Command Line Tools User Guide "TRACE" chapter. >>>>> INFO:Timing:3386 - Intersecting Constraints found and resolved. For more >>>>> information, see the TSI report. Please consult the Xilinx Command >>>>> Line >>>>> Tools User Guide for information on generating a TSI report. >>>>> INFO:Timing:3284 - This timing report was generated using estimated delay >>>>> information. For accurate numbers, please refer to the post Place and >>>>> Route >>>>> timing report. >>>>> Number of Timing Constraints that were not applied: 3 >>>>> >>>>> Asterisk (*) preceding a constraint indicates it was not met. >>>>> This may be due to a setup or hold violation. >>>>> >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> Constraint | Check | Worst Case >>>>> | Best Case | Timing | Timing >>>>> | | Slack >>>>> | Achievable | Errors | Score >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> * PERIOD analysis for net "mad_corr_beam_x6 | SETUP | >>>>> -3.440ns| 9.690ns| 113| 272325 >>>>> 4_adc_fab_phase_gen/mad_corr_beam_x64_adc | HOLD | >>>>> -0.179ns| | 6891| 366231 >>>>> _fab_phase_gen/CLK0_BUF" derived from PE | | >>>>> | | | >>>>> RIOD analysis for net "mad_corr_beam_x64_ | | >>>>> | | | >>>>> adc/fab_clk1" derived from NET "mad_corr_ | | >>>>> | | | >>>>> beam_x64_adc/mad_corr_beam_x64_adc/x64_ad | | >>>>> | | | >>>>> c_infrastructure_inst/adc_clk_ibufds" PER | | >>>>> | | | >>>>> IOD = 4.1667 ns HIGH 50% multiplied by 1. | | >>>>> | | | >>>>> 50 to 6.250 nS and duty cycle corrected t | | >>>>> | | | >>>>> o HIGH 3.125 nS duty cycle corrected to | | >>>>> | | | >>>>> 6.250 nS HIGH 3.125 nS | | >>>>> | | | >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> * TS_mgt_clk_0 = PERIOD TIMEGRP "mgt_clk_0" | SETUP | >>>>> 3.803ns| 2.597ns| 0| 0 >>>>> 156.25 MHz HIGH 50% | HOLD | >>>>> -1.513ns| | 218| 146110 >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> * TS_mgt_clk_mult_2_b = PERIOD TIMEGRP "mgt | SETUP | >>>>> 5.500ns| 0.900ns| 0| 0 >>>>> _clk_mult_2_b" 156.25 MHz HIGH 50% | HOLD | >>>>> -0.204ns| | 18| 3672 >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> NET "mad_corr_beam_x64_adc/mad_corr_beam_ | MINLOWPULSE | >>>>> 0.566ns| 3.600ns| 0| 0 >>>>> x64_adc/x64_adc_infrastructure_inst/adc_c | | >>>>> | | | >>>>> lk_ibufds" PERIOD = 4.1667 ns HIGH 50% | | >>>>> | | | >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> PERIOD analysis for net "mad_corr_beam_x6 | SETUP | >>>>> 5.132ns| 1.118ns| 0| 0 >>>>> 4_adc/fab_clk1" derived from NET "mad_co | HOLD | >>>>> 0.195ns| | 0| 0 >>>>> rr_beam_x64_adc/mad_corr_beam_x64_adc/x64 | MINLOWPULSE | >>>>> 2.249ns| 4.000ns| 0| 0 >>>>> _adc_infrastructure_inst/adc_clk_ibufds" | | >>>>> | | | >>>>> PERIOD = 4.1667 ns HIGH 50% multiplied b | | >>>>> | | | >>>>> y 1.50 to 6.250 nS and duty cycle correct | | >>>>> | | | >>>>> ed to HIGH 3.125 nS | | >>>>> | | | >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> TS_sys_clk_n = PERIOD TIMEGRP "sys_clk_n" | MINPERIOD | >>>>> 1.668ns| 8.332ns| 0| 0 >>>>> 100 MHz HIGH 50% | | >>>>> | | | >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> PERIOD analysis for net "mad_corr_beam_x6 | SETUP | >>>>> 2.874ns| 1.292ns| 0| 0 >>>>> 4_adc/mad_corr_beam_x64_adc/x64_adc_infra | HOLD | >>>>> 0.148ns| | 0| 0 >>>>> structure_inst/adc_clk_dcm" derived from | MINPERIOD | >>>>> 1.945ns| 2.221ns| 0| 0 >>>>> NET "mad_corr_beam_x64_adc/mad_corr_beam | | >>>>> | | | >>>>> _x64_adc/x64_adc_infrastructure_inst/adc_ | | >>>>> | | | >>>>> clk_ibufds" PERIOD = 4.1667 ns HIGH 50% | | >>>>> | | | >>>>> duty cycle corrected to 4.167 nS HIGH 2. | | >>>>> | | | >>>>> 083 nS | | >>>>> | | | >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> NET "epb_cs_n_IBUF" MAXDELAY = 4 ns | MAXDELAY | >>>>> 4.000ns| 0.000ns| 0| 0 >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> TS_RAM_FF = MAXDELAY FROM TIMEGRP "RAMSOU | SETUP | >>>>> 4.580ns| 1.670ns| 0| 0 >>>>> RCE" TO TIMEGRP "FFDEST" 6.25 ns DATAPATH | HOLD | >>>>> 1.175ns| | 0| 0 >>>>> ONLY | | >>>>> | | | >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> NET "mad_corr_beam_x64_adc/mad_corr_beam_ | N/A | >>>>> N/A| N/A| N/A| N/A >>>>> x64_adc/x64_adc_infrastructure_inst/adc_c | | >>>>> | | | >>>>> lk_ibufds" PERIOD = 4.1667 ns HIGH 50% | | >>>>> | | | >>>>> ---------------------------------------------------------------------------------------------------------- >>>>> >>>>> >>>>> Derived Constraint Report >>>>> Derived Constraints for >>>>> mad_corr_beam_x64_adc/mad_corr_beam_x64_adc/x64_adc_infrastructure_inst/adc_clk_ibufds >>>>> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+--- >>>>> ----------+ >>>>> | | Period | Actual Period >>>>> | Timing Errors | Paths >>>>> Analyzed | >>>>> | Constraint | Requirement >>>>> |-------------+-------------|-------------+-------------|-------------+-------------| >>>>> | | | Direct | >>>>> Derivative | Direct | Derivative | Direct | >>>>> Derivative | >>>>> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+--- >>>>> ----------+ >>>>> |mad_corr_beam_x64_adc/mad_corr_| 4.167ns| 3.600ns| >>>>> 6.460ns| 0| 7004| 0| >>>>> 1035514| >>>>> |beam_x64_adc/x64_adc_infrastruc| | | >>>>> | | | | >>>>> | >>>>> |ture_inst/adc_clk_ibufds | | | >>>>> | | | | >>>>> | >>>>> | mad_corr_beam_x64_adc/mad_corr| 4.167ns| 2.221ns| >>>>> N/A| 0| 0| 4528| >>>>> 0| >>>>> | _beam_x64_adc/x64_adc_infrastr| | | >>>>> | | | | >>>>> | >>>>> | ucture_inst/adc_clk_dcm | | | >>>>> | | | | >>>>> | >>>>> | mad_corr_beam_x64_adc/fab_clk1| 6.250ns| 4.000ns| >>>>> 9.690ns| 0| 7004| 1375| >>>>> 1029611| >>>>> | mad_corr_beam_x64_adc_fab_pha| 6.250ns| 9.690ns| >>>>> N/A| 7004| 0| 1029611| >>>>> 0| >>>>> | se_gen/mad_corr_beam_x64_adc_| | | >>>>> | | | | >>>>> | >>>>> | fab_phase_gen/CLK0_BUF | | | >>>>> | | | | >>>>> | >>>>> +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+--- >>>>> ----------+ >>>>> >>>>> 3 constraints not met. >>>>> INFO:Timing:2761 - N/A entries in the Constraints list may indicate that >>>>> the >>>>> constraint does not cover any paths or that it has no requested value. >>>>> >>>>> >>>>> >>>>> Mapping completed. >>>>> See MAP report file "system_map.mrp" for details. >>>>> Problem encountered during the packing phase. >>>>> >>>>> Design Summary >>>>> -------------- >>>>> Number of errors : 1 >>>>> Number of warnings :2201 >>>>> ERROR:Xflow - Program map returned error code 2. Aborting flow >>>>> execution... >>>>> gmake: *** [__xps/system_routed] Error 1 >>>>> >>>>> -- >>>>> Andrea Mattana >>>>> >>>>> I.N.A.F. - Istituto di Radioastronomia >>>>> Radiotelescopi di Medicina >>>>> Via Fiorentina, 3513 - 40059 Medicina (Bo) >>>>> Tel. 051/6965834 Fax. 051/6965810 >>>>> >>>> >>>> >>> >>> >>> >>> -- >>> Andrea Mattana >>> >>> I.N.A.F. - Istituto di Radioastronomia >>> Radiotelescopi di Medicina >>> Via Fiorentina, 3513 - 40059 Medicina (Bo) >>> Tel. 051/6965834 Fax. 051/6965810 >>> > > > > -- > Andrea Mattana > > I.N.A.F. - Istituto di Radioastronomia > Radiotelescopi di Medicina > Via Fiorentina, 3513 - 40059 Medicina (Bo) > Tel. 051/6965834 Fax. 051/6965810 -- Andrea Mattana I.N.A.F. - Istituto di Radioastronomia Radiotelescopi di Medicina Via Fiorentina, 3513 - 40059 Medicina (Bo) Tel. 051/6965834 Fax. 051/6965810
