Hi, Joe, On Oct 15, 2013, at 5:20 PM, Kujawski, Joseph wrote:
> 1) Why is the sample rate set to '1' rather than 1/(User IP Clock Rate)? I'm not sure which "sample rate" setting you're referring to, but I think this might be related to the Simulink "sample rate" setting and not the actual ADC sample rate or the fabric clock rate. > 2) Can multiple clock rates be set/used in the ROACH2 board? For example, > can we use the ADC clock for ADC captures and a (much) faster clock for the > data processing portion of the algorithm? Yes and no. In theory, yes, multiple clocks could be used on a ROACH2 board and, in theory, System Generator even has ways of dealing with multiple asynchronous clock domains in one FPGA design, but in practice the CASPER toolflow is not setup to handle multiple clock domains (at least not for the user fabric clock). How fast are you sampling and how fast do you want to run the DSP part of the algorithm? Dave
