Hi all,
I've just started working on porting a design I had done for a ROACH 1 up to
ROACH 2. The design is based off of the 64ADCx64-12 running at 50Msps with a
handful of VHDL/Coregen blocks. I've finally got all the green/yellow blocks
updated for ROACH 2 so that it will actually synthesize, but now I'm getting a
bunch of timing errors, all component switching limit error. I'm comfortable
clearing up setup/hold errors by pipelining and whatnot, but I've never had
component switching errors, so I'm not even sure where to begin to diagnose and
fix them (or even what they really mean...) Does anyone have any general tips
or references for these kind of timing errors?
Thanks,
Jay Brady
