Hey all, sorry for the late reply. I saw this some time ago as well. If you look at the Virtex 6 DC/Switching characteristics [1], you can see component switching limits on the hardware we're developing to. Naturally, you can't pass timing if you intend to operate faster than those speeds. Unfortunately, Xilinx omits several restrictions from that listing. Specifically, you need to have at least one register in every path which is in use for the DSP48 to operate at full speed. In this case, it looks like your AREG could use another pipeline register, although the problem is most troublesome with the D register (which gets no mention whatsoever in the tools). You could resolve this by hacking the complex multiply block such that the DSP carries one extra latency in that part, reducing the external latency by 1. If conditions require, you might have to change other components at higher hierarchical levels, if there isn't enough latency to absorb.
Finally, if this is your worst-case slack (-0.092 ns), I frankly just wouldn't worry about it. There are a number of pessimistic assumptions made in the timing analysis of these designs, and if you can garuntee that you won't be operating at 75C, 0.95V, your designs will operate somewhat faster. Do check what your best-case achievable period is! [1] http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf On Mon, Feb 24, 2014 at 3:56 PM, Jack Hickish <[email protected]> wrote: > Hi Jay, > > Component switching limits test that individual components of your > design are running within their specified operating frequency > parameters -- a few brief posts are here -- > > http://forums.xilinx.com/t5/Timing-Analysis/component-switching-limit/m-p/73419 > -- so to fix them you basically just have to find the specific > component which is unhappy, and work out how to use it within it's > allowed ranges. > > I've sometimes seen these errors with misconfigured MMCMs and things > like that. Does the timing report shed any light on where you are > getting these errors? If it's something in the ADC yellow block (which > would surprise me a little because I've compiled for 50MSa on ROACH 2) > then I'll try and recreate your error and fix it. > > Cheers, > Jack > > On 24 February 2014 23:30, Jay Brady <[email protected]> wrote: > > Hi all, > > > > I've just started working on porting a design I had done for a ROACH 1 > up to > > ROACH 2. The design is based off of the 64ADCx64-12 running at 50Msps > with a > > handful of VHDL/Coregen blocks. I've finally got all the green/yellow > blocks > > updated for ROACH 2 so that it will actually synthesize, but now I'm > getting > > a bunch of timing errors, all component switching limit error. I'm > > comfortable clearing up setup/hold errors by pipelining and whatnot, but > > I've never had component switching errors, so I'm not even sure where to > > begin to diagnose and fix them (or even what they really mean...) Does > > anyone have any general tips or references for these kind of timing > errors? > > > > Thanks, > > Jay Brady > >
