Hi Andres,

I've found the source of your problem and it's a bug (my fault)
originating from the use of ZDOK1 without ZDOK0.

A really quick way to avoid this error is to change your single ADC5G
to ZDOK0. However if you can't do that I have pushed a fix for this to
the sma-wideband mlib_devel fork on Github, located here:

https://github.com/sma-wideband/mlib_devel

See commit d4954fd. It's up to you on whether to re-clone using that
repository, or add it as a remote and merge in the changes. However if
you prefer to just apply a patch I have attached a patch file that can
be applied (using git apply) in your mlib_devel root directory which
should fix your issue.

Best,
Rurik

On Wed, May 7, 2014 at 4:15 PM, Andres Alvear <[email protected]> wrote:
> Hi Rurik,
>
> Yes, I am trying that setup.
>
> The output of the commands is the following:
>
> root@roach-MS-7845:/opt/mlib_devel# git rev-parse --short HEAD
> a8c43a8
> root@roach-MS-7845:/opt/mlib_devel# git remote -v
> origin    git://github.com/ska-sa/mlib_devel.git (fetch)
> origin    git://github.com/ska-sa/mlib_devel.git (push)
>
> Thanks,
> Andres
>
>
> 2014-05-07 16:01 GMT-04:00 Primiani, Rurik <[email protected]>:
>
>> Hi Andres,
>>
>> Are you using a single ADC5G in the ZDOK1 slot? If so, why?
>>
>> Can you give the output of the following commands from your mlib_devel
>> root directory:
>>
>> $ git rev-parse --short HEAD
>> $ git remote -v
>>
>> Thanks,
>> Rurik
>>
>> On Wed, May 7, 2014 at 3:56 PM, Andres Alvear <[email protected]>
>> wrote:
>> >
>> > Hi Rurik,
>> >
>> > I am using Xilinx 14.5 version and the last time I updated the libraries
>> > was
>> > november 2013.
>> >
>> > Do you think that's the problem?
>> >
>> > Thanks,
>> > Andres
>> >
>> >
>> > 2014-05-07 15:48 GMT-04:00 Primiani, Rurik <[email protected]>:
>> >
>> >> Hi Andres,
>> >>
>> >> Which version of mlib_devel are you using?
>> >>
>> >> Thanks,
>> >> Rurik
>> >>
>> >> On Wed, May 7, 2014 at 3:43 PM, Andres Alvear
>> >> <[email protected]>
>> >> wrote:
>> >> > I am trying to compile a wideband spectrometer (like in tutorial 3)
>> >> > for
>> >> > ROACH 2, using a ADC1x5000-8 in the 1:1 demux version.
>> >> >
>> >> > I'm using the asiaa_adc5g yellow block in simulink model with the
>> >> > following
>> >> > configuration:
>> >> >
>> >> > Input mode: One-Channel -- A
>> >> > ADC Board ZDOK1
>> >> > Internal Demux:  1:1
>> >> > ADC Clock Rate: 800 MHz
>> >> >
>> >> > I get the following compilation error:
>> >> >
>> >> > ERROR:EDK:4072 - INSTANCE: tutorial3roach2_v2_asiaa_adc5g, PORT:
>> >> > datain_pin
>> >> > -
>> >> >    port is driven by a sourceless connector -
>> >> >
>> >> >
>> >> >
>> >> > /home/roach/Desktop/workspace/tutorial3roach2_v2/XPS_ROACH2_base/system.mhs
>> >> >    line 279
>> >> > ERROR:EDK:4072 - INSTANCE: tutorial3roach2_v2_asiaa_adc5g, PORT:
>> >> > datain_tap
>> >> > -
>> >> >    port is driven by a sourceless connector -
>> >> >
>> >> >
>> >> >
>> >> > /home/roach/Desktop/workspace/tutorial3roach2_v2/XPS_ROACH2_base/system.mhs
>> >> >    line 279
>> >> > ERROR:EDK:4072 - INSTANCE: tutorial3roach2_v2_asiaa_adc5g, PORT:
>> >> > tap_rst
>> >> > -
>> >> > port
>> >> >    is driven by a sourceless connector -
>> >> >
>> >> >
>> >> >
>> >> > /home/roach/Desktop/workspace/tutorial3roach2_v2/XPS_ROACH2_base/system.mhs
>> >> >    line 279
>> >> > Completion time: 0.00 seconds
>> >> > ERROR:EDK:440 - platgen failed with errors!
>> >> > gmake: *** [implementation/system.bmm] Error 2
>> >> > ERROR:EDK -
>> >> >    Error while running "gmake -f system.make bits".
>> >> > Error using gen_xps_files (line 638)
>> >> > XPS failed.
>> >> >
>> >> > Cheers,
>> >> > Andres
>> >> >
>> >> >
>> >
>> >
>> >
>
>
diff --git a/xps_base/XPS_ROACH2_base/system.mhs b/xps_base/XPS_ROACH2_base/system.mhs
index 9031a14..c552193 100644
--- a/xps_base/XPS_ROACH2_base/system.mhs
+++ b/xps_base/XPS_ROACH2_base/system.mhs
@@ -370,9 +370,9 @@
 #IF# (strcmp(get(b,'type'),'xps_adc5g'))  && get(b,'use_adc1')# PORT adc1_clk              = adc1_clk
 #IF# (strcmp(get(b,'type'),'xps_adc5g'))  # #
 #IF# (strcmp(get(b,'type'),'xps_adc5g'))  # # IDELAY control signals for adc1
-#IF# (strcmp(get(b,'type'),'xps_adc5g'))  && get(b,'use_adc0')# PORT adc1_tap_rst          = adc1_tap_rst
-#IF# (strcmp(get(b,'type'),'xps_adc5g'))  && get(b,'use_adc0')# PORT adc1_datain_pin       = adc1_datain_pin
-#IF# (strcmp(get(b,'type'),'xps_adc5g'))  && get(b,'use_adc0')# PORT adc1_datain_tap       = adc1_datain_tap
+#IF# (strcmp(get(b,'type'),'xps_adc5g'))  && get(b,'use_adc1')# PORT adc1_tap_rst          = adc1_tap_rst
+#IF# (strcmp(get(b,'type'),'xps_adc5g'))  && get(b,'use_adc1')# PORT adc1_datain_pin       = adc1_datain_pin
+#IF# (strcmp(get(b,'type'),'xps_adc5g'))  && get(b,'use_adc1')# PORT adc1_datain_tap       = adc1_datain_tap
 #IF# (strcmp(get(b,'type'),'xps_adc5g'))  # #
 #IF# (strcmp(get(b,'type'),'xps_adc5g'))  #END
 

Reply via email to