Hi Edgardo
If you're after a decimating FIR filter, then you can use the mixer and
dec_fir.
Here's a screenshot showing a design that selects 200 MHz bandwidth out
of 400 MHz; that is, 4 parallel real-valued --> 1 complex-valued stream:
https://dl.dropboxusercontent.com/u/9870263/dec-fir.png
Note that the dec_fir is a little picky about the length of your filter
(eg 100 vs 101 taps). I just used the fdatool for the coefficients
(sounds like you're already familiar with this).
Using this, you could convert your 8 parallel real inputs to 1 complex
output, for an overall bandwidth reduction of 4x.
Regards
Danny
Edgardo Antonio <mailto:[email protected]>
June 3, 2014 at 12:27 PM
Hi everybody.
I have a problem building a digital filter before the data enter to
the PFB on my design. I need to design an FIR band pass filter but i
don know if there is a well known way to do this (maybe there is a
block pre-designed).
i found a FIR compiler on the xilinx blockset and i load the fir
coefficients from the fda tool without problems. I Have 8 samples in
parallel coming from the ADC each clock FPGA clock cicle.
it seems to me the problem is that the xilinx FIR compiler is
filtering each path independently, in other words not considering the
8 inputs in parallel like 8 samples of a signal each taken at the same
rate sample.
i hope some one understand the problem and could have a solution.
Have anyone has the same problem? Thank you
--
/Edgardo Huaracán Durán/
/
/
/Memorista Observatorio Astronómico Nacional
/
/
Universidad de Chile/
