hi edgardo, when you see two tones instead of one, are you doing a complex FFT (complex in, complex out), or are you doing a real FFT (real in, complex out).
you need to do a complex FFT to resolve negative and positive frequencies. best wishes, dan On Fri, Jun 6, 2014 at 9:08 AM, Edgardo Huaracán Durán < [email protected]> wrote: > HI Danny, Thank you very much for your answer. It helped me a lot. > > but i'm still have some problems. when i use the real part of the complex > output of the dec_fir block, i get an overall bandwidth reduction of 8x > without problem. the problem is when i use the real and imaginary parts for > an overall bandwidth reduction of 4, i see two tones > instead of one, so i get a reduction of bandwidth but i can't get rid of > this extra tone. > so i can't have a reduction of 4x on my bandwidth, how can i overcome this > problem? > > thanks in advance. regards. > > > 2014-06-03 13:13 GMT-04:00 Danny Price <[email protected]>: > >> Hi Edgardo >> >> If you're after a decimating FIR filter, then you can use the mixer and >> dec_fir. >> >> Here's a screenshot showing a design that selects 200 MHz bandwidth out >> of 400 MHz; that is, 4 parallel real-valued --> 1 complex-valued stream: >> https://dl.dropboxusercontent.com/u/9870263/dec-fir.png >> >> Note that the dec_fir is a little picky about the length of your filter >> (eg 100 vs 101 taps). I just used the fdatool for the coefficients (sounds >> like you're already familiar with this). >> >> Using this, you could convert your 8 parallel real inputs to 1 complex >> output, for an overall bandwidth reduction of 4x. >> >> Regards >> Danny >> >> Edgardo Antonio <[email protected]> >> June 3, 2014 at 12:27 PM >> Hi everybody. >> >> I have a problem building a digital filter before the data enter to the >> PFB on my design. I need to design an FIR band pass filter but i don know >> if there is a well known way to do this (maybe there is a block >> pre-designed). >> >> i found a FIR compiler on the xilinx blockset and i load the fir >> coefficients from the fda tool without problems. I Have 8 samples in >> parallel coming from the ADC each clock FPGA clock cicle. >> >> it seems to me the problem is that the xilinx FIR compiler is filtering >> each path independently, in other words not considering the 8 inputs in >> parallel like 8 samples of a signal each taken at the same rate sample. >> >> i hope some one understand the problem and could have a solution. >> >> Have anyone has the same problem? Thank you >> -- >> *Edgardo Huaracán Durán* >> >> >> *Memorista Observatorio Astronómico Nacional* >> >> *Universidad de Chile* >> >> > > > -- > *Edgardo Huaracán Durán* > > > *Memorista Observatorio Astronómico Nacional* > > *Universidad de Chile* > >
