Hi Ho-Cheung, At present, the sync signal can only be supplied by the FPGA, the external sync input is wired directly to the FPGA on the board (i.e. not to the ADC chip). Generally the start-up procedure is to set the ADC into test ramp mode, sync it, and the use the ramp to calibrate the MMCM. This can be done with some Python code and has been discussed extensively on the mailing list so I won't repeat it. See the read me here: https://github.com/sma-wideband/adc_tests.
If you want to sync across multiple boards using the same signal then you'll have to use an external pulse rerouted through the FPGA and back into the ADC chip. This is not presently possible without manually editing VHDL code. However this was discussed just last week at the workshop and is on a short list of changes to be implemented in the near future. Best, Rurik On Tue, Jun 17, 2014 at 1:28 AM, Ho-Cheung Ng <[email protected]> wrote: > Hi All, > > We have be trying to use ADC1x5000-8 with roach2 and we noticed that the > sync signal has to be supplied after power up or power configuration. We > would like to ask if it is possible to have that signal driven by the FPGA. > If so, could you give me suggestions or comments on how to make it work? We > deeply appreciate any help or suggestions. > > Best, > Ho-Cheung Ng > > > -- > Ho-Cheung Ng > M.Phil. Candidate > Computer Architecture and System Research (CASR) Lab > Department of Electrical and Electronic Engineering > The University of Hong Kong > >
