I just found an error in the design:-) I will correct it and send the new results.
RP 2014-10-05 19:46 GMT-06:00 Rolando Paz <[email protected]>: > Thanks for the clarification Glenn. > > The design I'm trying to run is attached. > > I am expecting a result like this: > > Input a --> Output aa > Input b --> Output bb > Input c --> Output cc > Input d --> Output dd > > Am I wrong? > > Best Regards > > Rolando Paz > > > > > 2014-10-05 19:09 GMT-06:00 G Jones <[email protected]>: > > It looks right, the biplex real 2x core interleaves the outputs to >> maintain a constant data flow. >> On Oct 5, 2014 8:49 PM, "Rolando Paz" <[email protected]> wrote: >> >>> Is this behavior normal? >>> >>> What happened with output 2 and 4? >>> >>> Best Regards >>> >>> Rolando Paz >>> >> >
