Hi Jack, Not sure if this will help, but in Planahead I would try to click and drag that LUT as close as possible to each of the outputs. And if that doesn't help or makes it worse, you could also try to duplicate the logic going to each of those outputs, forcing separate LUTs to be used.
Cheers, Mark On Thu, Dec 4, 2014 at 10:48 AM, Jack Hickish <jackhick...@gmail.com> wrote: > Hi all, > > This is something I've been fighting with for a while now, and I wonder if > anyone on this maillist has any insight (because I'm pretty sure I may just > be doing something wrong with the tools). > > The problem: > I'm playing with a ROACH2 design that (sometimes) compiles at 312 MHz. > However, every now and then I'll make a small change to the design and the > compile will fail timing catastrophically, with paths failing sometimes > with -2 ns (or worse) slack. > When I look at the failing path(s), the delays are usually ~80% routing. > I'll see a signal take a huge detour to use a shift register in some > arbitrary location on the chip. Upon closer inspection of the relevant SRL, > it appears that the LUT concerned is being used for two signal paths, one > on the O5 output, one on the O6. The result seems to be that it is poorly > placed for both it's roles. > > I'm only using ~50% of the slices and about 30% of the registers / luts on > the FPGA, and there are plenty of sensibly located SLICEMs the placer could > use if it so desired. I've switched lut combining off (with the -lt flag), > in planahead which doesn't seem to have made any difference. > > Can anyone offer me any words of advice / wisdom which might reduce my > confusion at what's going on (or, even better, help me solve the problem)? > > Despairingly yours, > Jack > > >
